NC State University ECE Dept.

Architecture Research for PErformance, Reliability, and Security

Tutorial at  HCPA 2007

Practical Cache Performance Modeling for Computer Architects

Yan Solihin, NCSU

Fei guo, NCSU

Thomas Puzak, IBM Research

Phil Emma, IBM Research


Time: Sunday morning, Feb 11, 2007

Place: Phoenix, Arizona (in conjunction with the 13th International Symposium on High Performance Computer Architecture (HPCA-13)

Important dates: TBD (you can also check at HPCA website)

Presentation Slides


Cache designs are increasingly critical to the overall performance of computer systems. The ever-increasing memory wall problem means that a single memory access which right now costs hundreds of processor cycles will keep increasing. Furthermore, the trend in hardware design in placing multiple processor cores on a chip, coupled with the trend of increasing software complexity and the number of software layers point to a significant capacity pressure in caches for years to come. Consequently, understanding the impact of various aspects of cache design is crucial in ensuring good overall system performance. Unfortunately, current practices for evaluating cache performance rely almost solely on cycle-accurate simulation, which is costly to run and offers insufficient insights into the relationship between application behavior and cache parameters.

The purpose of this tutorial is to bring together recent advances in analytical and empirical modeling technology for cache performance, and present them to computer architect designers and researchers, so that they can benefit from the technology. In particular, the tutorial will not only present the models, but also present how the models can be used in practice for cache design exploration. Some of the tools will be released and their usage and demo will also be presented.


Tentative List of Topics:


Introduction - 5 mins

Capturing temporal locality behavior - 25 mins

- Stack distance profiling

- Circular sequence profiling

Modeling the Impact of Cache Parameters on Performance - 30 mins

- Predicting cache miss rates across different cache sizes and associativities

- Prediction cache miss rates across different replacement policies

Modeling the Impact of Cache Interference in Multi-core and multi-tasked system  - 60 mins

- Predicting the impact of cache sharing in CMP

- Predicting the impact of context switches on cache states

Analysis of the effects of miss clustering on the cost of a cache miss ¨C 60 mins

- Describe new technique to measure the cost of a cache miss.

- Display graphs showing cost of each miss versus cluster size

- Use graphs to analyze prefetching algorithm

- Present theory that describes miss cluster patterns versus cost


The tutorial materials will be based on prior publications (roughly 60%) as well as ongoing research work (roughly 40%). When materials are taken from prior publications, the emphasis will be beyond technical description of the models, but also on how the models can be used in practice, and on case studies that show useful insights obtained using the models.


PresentersĄŻ Bios


Yan Solihin received his MS and PhD in Computer Science from the University of Illinois at Urbana-Champaign in 1999 and 2002. He is currently an assistant professor at the Department of Electrical and Computer Engineering at the North Carolina State University. He has published more than 20 papers in computer architecture and performance modeling. His research interests include design, modeling, and implementation of chip multiprocessor memory hierarchy systems and architecture support for security and software reliability. He has released released Scaltool, a performance modeling software for pinpointing parallel program scalability bottlenecks, and Fodex, a forensic document examination toolset. He is a recipient of 2005 IBM Faculty Partnership Award, 2004 NSF Faculty Early Career Award, and 1997 AT&T Leadership Award. He is a member of the IEEE and ACM SIGMICRO.

Thomas Puzak received a B. S. in Mathematics and M. S. in Computer Science from the University of Pittsburgh and a Ph. D. in Electrical and Computer Engineering from the University of Massachusetts.  Since joining IBM in 1970, he has spent over thirty years working in IBM Research.  While at IBM he received Technical Achievement, Outstanding Contribution, and Innovation Awards, served as Chairman of the Computer Architecture Special Interest Group at the T. J. Watson Research Center and holds more than 30

patents, on topics concerning processor and memory design.


Phil EmmaĄŻs bio here