Spring 2003

Course Web Page

(For use by On-Campus students)

(Distance Education [VBEE and NTU students], please use THIS PAGE.)

Instructor : Dr. Paul D. Franzon, paulf_franzon@ncsu.edu

Office Hours : Tuesday, Thursday 6.00 – 7.00 (in DAN 307)

(Note : My regular office is EGRC 443.)

Class Time : Tuesday, Thursday 7.30 – 8.45 DAN 429

Teaching Assistants

TBD, responsible for maintaining grade sheets

TBD , responsible for off-campus students

TBD , lead on ECE 520 project

TBD, lead on ECE 464 project

Laboratory Times

All labs are held in DAN 253.

§ TBD

Laboratory attendance is desirable but not required. Note that little help will be available outside the labs.

Note, you also have remote access to dialup.eos.ncsu.edu and remote.eos.ncsu.edu. Check out http://www.eos.ncsu.edu/remoteaccess/ to find out how to access NCSU computers remotely.

Important Dates

Mid-Term Exam : Monday, February 24

Final Exam : Monday, May 5

Class Objectives. Functionally, the objective of ECE 520 is to prepare you to be an ASIC or FPGA designer in industry. To this end we will focus on how to execute and capture a large complex design in an HDL, using Verilog as the main example. We will also cover a number of other issues important to ASIC designers, including Verification, Design For Test, low power design, etc. You will demonstrate your ability to design a complex ASIC or FPGA function via a major project.

Functionally, the objective of ECE 464 is to give the student advanced preparation in digital system design using HDLs, and introduce other, related, issues. The much simpler project does not fully prepare you to be an industrial designer.

Class Syllabus

Lecture Notes

Supplied Formats:

§ 1 up : One slide per sheet

§ 2 up : 2 slides per sheet – requires least paper

§ notes : One slide per sheet but bottom half of sheet blank (Best format for note taking in class, and the overall best in my opinion)

Notes:

Introduction in one-up, and two-up formats (notes format not really useful here)
Timing in one-up, two-up and notes formats

Need nor2_out.pdf and dff_out.pdf
Supplemental note fixing some errors

Verilog1 in one-up, two-up and notes formats
Verilog2 in one-up, two-up and notes formats
Complexity in one-up, two-up and notes formats
Verification in one-up, two-up and notes formats
Synthesis in one-up, two-up and notes formats
Design For Test in one-up, two-up and notes formats
CMOS in one-up, two-up and notes formats

Homeworks

Homework 1

Needed files : and2_out.pdf, dff_out.pdf, dsel2_out.pdf, or2_out.pdf

Tutorial

Needed files : count.v, test.v, count1.sc, count2.sc, and rename this file as .synopsys_dc.setup

Needed files : badFSM.v, badFSM_test.v

Homework 2

You will need the files above for Q 5.

Project Description

Past Exams

0.25 mm Library

A 0.25 mm library can be found in the directory http://www.ece.ncsu.edu/asic/tutorials/tsmc025_lib/ . Make sure to copy the synopsys setup file from there. There is a tutorial in there for Place and Route in Silicon Ensemble. (Place and route is not expected.) For reference, the .lib and .db files are uploaded in the cad445/local/TSMC025_deep directory.

Other Resources

A bulletin board will be established in wolfware. Please feel free to post questions (and answers) there. Often I find that many students have the same questions. Sharing these makes a lot of sense.
The recommended on-line Verilog reference guide can be found on the Sutherland Reference Guide Page
Sutherland has a number of other good Verilog resources.
http://www.verilog.net/ is another good resource.
Our list of local Cadence resources can be found on the NCSU Cadence Home Page
Links to other Universities, etc., can be found on the Cadence University Home Page
www.opencores.org has a number of complex IP cores.
www.visualverilog.com has a demo version of a “schematic” verilog capture tool.
AT&T has a free program for drawing FSMs