Module 13. Field Programmable Gate Arrays

Field Programmable Gate Arrays (FPGAs) are useful for building ASICs that do not require the performance levels that can be achievd in a standard cell ASIC. They incur substantially lower up-front engineering costs but cost more per part than a standard cell ASIC. On the whole, the RTL-based design methodology for an FPGA is the same as for a standard cell ASIC. However, it is useful to understand the (limited) available resources available in an FPGA and how to design your logic to maximally use them. With this approach, you are more likely to fit a large complex design onto a single FPGA.

Objectives

• Identify typical architectural features available in FGPAs.
• Understand that if you tailor your design to the available resources you are more likely to meet speed and cost requirements.

Key Points

• FPGA resources typically include programmable logic blocks, programmable interconnect and special purpose functions such as CPUs and arithmetic functions.
• Tailoring your design to maximally use the provided special functions increases your chance of meeting design targets.
• Interconnect is limited in FPGAs and consumes considerable power. Try to select approaches that limit interconnect use.

PDF files:

• http://www.ece.ncsu.edu/asic/2009/docs/FPGA.pdf

PDF files are distributed in the links above. If you want the ppt version, please go to http://courses.ncsu.edu/ece520/lec/001/wrap/ . Note, this PPT version does NOT include answers to in-line questions.