TUTORIALS FAQ:
Q1)
When I write the command source read.tcl in the design vision command prompt it is giving me the warning
Can't read link_library file 'your_library.db'
A1)
Looks like you have not copied over the .synopsys_dc.setup file into the directory that you are working in OR have copied it over after invoking design_vision. You need to copy over the setup file and after that, invoke design_vision.
Q2)
While doing the iterative compilation with different values of clock period, should we create each design in a separate directory? (Which implies that one has to restart synopsys / design_vision in each directory ) If running each iteration in the same directory do we have to shut down and restart synopsys / design_vision between iterations in the same directory?
A2)
Nope. There is no need to do either. You must remain in the same directory and in the same session of design_vision while working on an incremental compilation with modified clocks. This is because the base design does not change. You attempt to compile with increasingly greater constraints on the compilation tool in an attempt to improve the performance of the synthesized netlist. This is done best by carrying over optimizations from one incremental compile to the next which requires you to keep the same session going until you are satisfied with your results or see no further improvement.
Q3)
I have what seems to be a legitimate design -- the test fixture runs just fine
-- but when I try to synthesize it, I'm having trouble when running the Constraints.tcl script.
Specifically, at replace_synthetic, I get the message: "Transferring design 'new_counter_DW01_dec_0' to database 'new_counter_DW01_dec_0.db'."
At check_design, I get:
"Warning: In design 'new_counter_DW01_dec_0', cell 'U1_B_7' does not drive any nets. (LINT-1)"
And at link, I get:
"Warning: Unable to resolve reference 'new_counter_DW01_dec_0' in 'new_counter'. (LINK-5)"
I have a feeling I can't just ignore these errors, and I don't get them when I build the unmodified counter. Can anyone suggest what I'm doing wrong?
A3)
the "does not drive any nets" error is due to outputs of modules you have left unconnected, or even internal signals you might have left unused. just try and remove all unwanted declarations or assignments from your design
Q4)
No matter which server I'm using, after I type the "> add synopsys" and "> design_vision" as the tutorial said, the commend line just show "Initializing...", then "design_vision-xg-t> design_vision-xg-t>" and "+ Suspended (tty input) design_vision". And the design_vision does not start all the time.
Does anyone know what's problem?
A4)
The reason you are getting the error is because you are invoking the tool by doing ">design_vision &". Please remove the "&" at the end. If you have already invoked design_vision with the "&" you can get to the "design_vision-xg-t>" prompt by typing "fg" on the terminal
Q5)
I got some errors while doing :
source CompileAnalyse.tcl
Error: Could not read the following target libraries:
osu018_stdcells_typ.db(UIO-3)
Then after i try to do the worst case i get these type of errors :
Error: Could not read the following target libraries: osu018_stdcells_typ.db UIO-3
Error: get_timing_paths requires a mapped design. UID-422
Error: Can't find lib_pin 'osu018_stdcells_slow/DFFPOSX1/D'. UID-109
Error: Value for list '' must have 1 elements. CMD-036
A5)
The .synopsys_dc.setup missing in the folder
Q6)
I am getting the following warnings when I am translating from fast to slow or vice versa... using the target_library, link_library and translate commands. I tried using the concatenating the library dw_foundation.sldb to the link and then translating them, but that didn't work. Why am I getting these warnings?
The last and the relevant warning is as follows:
Warning: There are conflicts between cells in libraries osu018_stdcells_slow:osu018_stdcells_slow.db (/afs/bp.ncsu.edu/dist/cadence_cdk/OSU018_StdCells/Slow) and osu018_stdcells_fast:osu018_stdcells_fast.db (/afs/bp.ncsu.edu/dist/cadence_cdk/OSU018_StdCells/Fast). (OPT-187)
Translating Design 'counter'
from the technology 'osu018_stdcells_slow' (cmos)
to the technology 'osu018_stdcells_slow' (cmos)
A6)
This is just information and not errors. Do not worry about them.
Q7)
Its given in the hw3.pdf that;
"It is best if you break the current script into 2 files; one up to the first report_timing and one after that. Enter the above commands by hand into design\_analyzer or dc\_shell" Cud someone pls elaborate these lines.
So how do we invoke design vision?
A7)
It is the same shell in which you source the tcl files. if you look at the files closely, they contain all the commands that you would normally type into that shell. The idea is to automate the compile/analyze till the first setup check, then manually make the clock as aggressive as possible, using incremental compile, and again automate the rest of the process of hold fix and post hold fix setup check, by invoking the second half of the script.
Q8)
Attempting to use the command;
write -f db -o tmp4.db gave the following error
Error: When using XG mode, it is recomended not to write your design in db format. Writing DB Format will increase the memory usage of the tool. If you still want to write a db, please re-issue the write command using the -xg_force_db option. UID-527
Is there any alternative for saving design ?
A8)
You could do what they suggest and do:
> write -f db -xg_force_db temp4.db
There is no need to save the db file if you have saved your output as a verilog file. You can just read in the netlist as:
> read_verilog -netlist .v
If you do want to use a binary format, a ddc format is better. The way you write it is
> write -format ddc -output counter_final.ddc
Q9)
could you please give the command for reading the .ddc file as well...i tried replacing the write with the read but it didnt work.
A9)
read_ddc counter.ddc
A suggestion. A good tool feature in design vision is that when you type a partial command (say read) on the prompt and then hit a tab, the tool gives you all the possible completions for it. Also, you can do "man read_ddc" to get more information on it.
Q10)
In my final timing reports (timing_min_fast_holdcheck.rpt & timing_min_slow_holdfixed.rpt) list "clock clock (rise edge)" as 0.0000 instead of my final clock period.
Is this a problem?
A10)
there are two sections in the timing report where the clock clock (rise edge) term comes into the picture.
- In the determination of the logic delay where the clock edge will be 0 given that we are determining the start time for timing analysis based off of that edge. We add logic delay to this time.
- To determine max arrival time for the logic, we begin by determine the time when the next pos edge of the clock is coming, i.e. the second clock clock (rise edge) which is equal to the clock period. From this we subtract the setup time, the external delays and the uncertainties in clock.
It is the second "clock clock (rise edge)" that should have a value.
The min reports do not require the clock period information. Remember that it is a minimum delay check i.e. hold check. The period does not matter for a hold check. What you are interested in checking is whether the transition of data with respect to a clock edge (i.e. just one edge) happens within hold time.
You will see in your lecture notes that the hold checks are all with respect to an edge and the data racing through and does not consider the time between clock edges (i.e. 1 clock period).
Q11)
On Page 18, there is a list of instructions to simulate and synthesize in ./SIMULATION/run_s and ./SYNTH/runs_s folders respectively. The note below there, seems to imply that we would not need to do the entire process followed in Tutorial 1 for this. I could not fully follow the note there.. Can you please explain it?
A11)
You need to run the synthesis to create the new counter_final.v from the ./SYNTH/run_s/ folder. The RTL_DIR variable changes to "../../HDL/run_s" which enables you to read the files from that folder from within the SYNTH/run_s/ folder.
The simulation need not be run in this case. But if you want to do so, you go into the ./SIMULATION/run_s/ folder and do (after initial setup per Tut 1):
> vlog ../../HDL/run_s/counter.v
> vlog ./test.v
> vsim -novopt test_fixture
Simulate in the SIMULATION/run_s/ directory and Synthesize in the SYNTH/run_s/ directory.
Q12)
when I run the vsim command(Ref Page 22, Tutorial 2), it goes to the vsim prompt, but then the compilation shows the following error message:
# ** Error: (vsim- 3448) /afs/bp.ncsu.edu/dist/cadence_cdk/OSU018_StdCells/Typical/osu018_stdcells.v(298): Setting negative specify check constraint (-90 ps) to zero.
Does this error mean that i need to try one of the other vsim commands listed.
A12)
That can be ignored. That happens because we are compiling a standard cell library that has timing constraints coded into it. Please confirm that the backward saif (counter_back.saif) file is still generated.
Q13)
since counter.v(HDL/run_s) and test.v(SIMULATION/run_s) are in different directories, how can i create a common vlib?
A13)
Just Point to them. There is no need for all your files to be in one directory. Assuming you want to do a simulation of your HDL before running it through the flow: work in ./SIMULATION/run_s and compile as
vlog ../../HDL/run_s/counter.v
vlog ./Test.v
Q14)
When I run the following command,
encounter #> restoreDesign counter_cts_trialroute.enc.dat/counter
I get a message saying, "no value given to parameter "design"to "restoreDesign" and then when I click on the mentioned buttons (Zoom full and Physical View), I see nothing.
A14)
Command is
restoreDesign counter_cts_trialroute.enc.dat/ counter
There is a space before counter.
Q15)
Some of the values generated after I run the command ./PAD_Flow.pl –op analyze –mod counter –clkname clock –period 10 –net ./SYNTH/run_f/counter_final.v are different as compared to what is given in the tutorial. Like I get
The Backward SAIF file (-saif) = ./SIMULATION/run_f/Top_back.saif instead of counter_back.saif and TOTAL AREA OF DESIGN TO BE ANALYZED (A): 11230 RESULTING DIMENSION OF CHIP (smallest multiple of 10 greater than sqrt(A)) = 110 instead of values 12102.2222222222 and 120 given in the tutorial. Kindly clarify.
A15)
This area reported is the total synthesis area of your design. Check to confirm correctness by determining the final area after synthesis of your design.
-saif is an input option which defaults to Top_back.saif unless your have specified something else as an input. The -saif option is not required to run this step in the flow (initial place and route). You will be using it as an input when you do your power analysis later in the Tutorial (step 3).
Q16)
On invoking,
vsim –novopt -c -pli $SYNOPSYS/linux/power/vpower/libvpower.so test_fixture
I get this error 8 times:
#**Error: (vsim -3448) /afs/bp.ncsu.edu/dist/cadence_cdk/OSU018_StdCells/Typical/osu018_stdcells.v(298): Setting negative specify check constraint (-90 ps) to zero.
1. 'Test_fixture' is correct.
2. Instance name 'u1' is correct in PAD_Flow.pl
3. No hold/setup violations post synthesis
??
A16)
That error is a message. Doing a "run -all" within the vsim #> prompt should still give you a saif file if there is no other error.
Do you see another error perhaps. There might be issues in the type of libvpower.so used i.e. linux/amd64. Please provide a snippet of the messages that pop up in the beginning when you run vsim -c -novopt ... .
You can find this information within the transcript file in the folder where you are running vsim.
Q17)
When I enter in:
design_vision-xg-t> ./PAD_Flow.pl -op analyze -mod counter -clkname clock -period 10 -net ./SYNTH/run_f/counter_final.v
I get the error :
Error: unknown command './PAD_Flow.pl' (CMD-005)
What am I doing wrong?
A17)
You are running the PAD_flow.pl script from within design_vision. Please exit design_vision. You need to be running it at the terminal.
Q18)
I have run the chmod command and tried to run the command ./PAD_Flow.pl -op setup. Nothing happens when I run chmod and then after running ./PAD_Flow.pl -op setup I get an error saying "./PAD_Flow.pl:command not found".
A18)
You have probably not made PAD_Flow.pl into an executable. You can do this by running the chmod 744 command specified in tutorial 2.
Q19)
for the 2nd sum of the homework where we have to write the code ...while saif creation of the same ...i changed the testbench by adding the required commands..however after giving the command vlog i get the following warning
* Warning: ./hw5test.v(10): Component name 'DUT' is not on a downward path.
and then while doing vsim i get an error in loading the design saying
Error: (vsim-3043) ./hw5test.v(10): Unresolved reference to 'DUT'.
what could be the reason?
A19)
What is the name of the design instance in your testbench? In tutorial 2, "DUT" corresponds to the instance name of the design that we are testing (as you can see in the testbench verilog file). If you have a different instance name for your design, you would need to change the above to the design instance name in your testbench.
Q20)
After I did the systhesis of my design, it showed a warning like this:
"Potential simulation-synthesis mismatch if index exceeds size of array 'packet'. (ELAB-349)"
I am not sure whether this kind of warning is acceptable.
A20)
yes it is. The reason for this is problem is that the total number of address locations in your memory/array is less than 2^(address width). Be sure to limit your addresses to less than the total number of locations. A good idea would be to write a $display in your testbench that displays an error message if the read/write address is greater than the total number of locations you have allocated.