Note: It is my view on homworks is that their main purpose is to prepare you for the project and tests. They are intended as learning experiences and the grade associated with them is mainly for motivation. My policy is that you can collaborate on homeworks but NOT copy solutions, or turn in "group" solutions, or individual copies of "group" solutions. We will look for copied solutions and will use on-line tools for checking copied solutions for Homework 5 and the project. If copying is detected, both of you will be cited for an academic violation. The idea is that you collaborate so you can learn from each other, not distribute the work load. In the project, you do have a partner to help reduce the workload BUT you are not to share code with other groups. Note, some of the points in the project are performance related. I suggest you NOT give away your good ideas.

The tutorials have an FAQ.

• Homework 1

  • Due in class, on Wednesday, January 14
  • Review of logic basics. If you need a refresher on these topics, there are numerous logic design books in the library, including Wakerley, Katz, etc. etc.
  • Should be started immediately

  Homework 2

  • Due in class, on Friday, January 21
  • Review of timing notes
  • Can be started after completing timing notes
• Homework 3

  • Due in class, on Friday, February 13
  • Basic design and synthesis

    Associated Tutorial and support files found here on the EDA wiki

  Project description (latest version - last amended Feb. 14, March 2 for supporting files)

  Supporting documents:

  Amended project description, highliting changes (last amended. Feb 1., 2009)

  Amended ECE 520 project files (March 2, 2009) : IOMEMv3.txt DICTMEMv3.txt expected_outputv3.txt

  Original project description

  XLS spreadsheet with the 520 memory example.

  match memory for 464 project - text and hex . Input for 464 project ( input464proj.txt ) Expected output (expected_output464.txt )

  Dictionary for 520 project, and input data stream. Expected output for this sream (expected_output520.txt )

• Homework 4

  • Due in class, on Wednesday, February 25
  • More sophisticated Verilog Examples. Make sure to review the tutorial 2 on the wiki .
  • Associated Bad FSM Verilog File and Test Fixture
  • Can be started after Verilog 2 and relevant portion of FSM notes
• Homework 5

  • Due in class, on Friday, March 20
  • See tutorial 3 on the eda wiki

  • Complex design strategies
  • Completes "tool chest" required for project
  • Can be started after completing Complexity and Hierarchy notes