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ECE 464/520 ASIC Design

Spring 2009

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Instructor: Dr. Paul D. Franzon

Teaching Assistants: Peter Gadfort (EOL TA); Mihir Shiveshwarkar (lead on 520 project); Kiran Gonsalves (lead on 464 project).

The on-line page pointing to the videos for this course can be found at: http://engineeringonline.ncsu.edu/mediasite/Homepages_Video/ece520_lectures.html

Class Schedule: Monday, Wednesday, Friday 3.50 – 5.05; EB 2, 1025. Classes are not held on all these days. Click here to find which days class is actually scheduled for.

Office Hours: Monday, Wednesday, Friday 2.30 – 3.30. (EB2 2116) (Only on days with scheduled classes)

Lab Hours: EB 2 Rooms 1014. These are open labs - more like TA office hours - anyone can attend, work and/or get help. I ask that you only do ECE 464 & ECE520 related computing work during these labs, please, especially if there are ece464/520 students waiting.

Times: 12:40 p.m. - 02:40 p.m. - Monday - Mihir Shiveshwarkar
12:15 p.m. - 02:15 p.m. - Thursday - Kiran Gonsalves
02:30 p.m. - 04:30 p.m. - Thursday - Peter Gadfort
12:15 p.m. - 02:15 p.m. - Friday - Kiran Gonsalves

EOL Students: Please contact Peter Gadfort to set up a lab time by appointment. He can do a phone consult, or if you have installed elluminate, he can do a virtual consult.

Course Syllabus

Message Board: I highly encourage you to use the Wolfware Bulletin Board instead of email for class questions.

Course Objectives:

  • To prepare the student to be an entry-level industrial standard cell ASIC or FPGA designer.

  • To give the student an understanding of issues and tools related to ASIC/FPGA design and implementation, including timing, performance and power optimization, verification and manufacturing test.

Course Outcomes:

  • Students will be able to design and synthesize a complex digital functional block, containing over 1,000 gates, using Verilog HDL and Synopsys Design Compiler.
  • Students will demonstrate an understanding of how to optimize the performance, area, and power of a complex digital functional block, and the tradeoffs between these.
  • Students will demonstrate an understanding of issues involved in ASIC design, including technology choice, design management, tool-flow, verification, debug and test, as well as the impact of technology scaling on ASIC design.