ECE 520 HomePage

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ECE 464/520 ASIC Design
Spring 2009
Class Notes

If you want a two-up or four-up format (to save paper), you can do this yourself in Adobe Acrobat PDF reader. (From the file menu, select "Print Setup" and click on "properties". The details from that point depend on the version you are running.)

This page contains the notes corresponding to the lectures recorded in Spring 2011. All other aspects of the class are to correspond to Spring 2011, and the links on the left have been changed appropriately.

Module 0. Revision Notes. This can only be viewed on-line via the video connection on the home page. It is lecture 003. This module quickly points out the prior knowledge assumed by this class and goes over timing diagrams and gate level design in more detail. If you felt that HW 1 was easy, you do not need to do watch this class. This content will not be taught in a "live" class.
Module 1. Introduction to ASIC Design
- Moores Law; ASIC Styles; CAD Flows
Module 2. Timing
- Clock Distribution; Flip-flop and latch timing; Timing-aware design
Module 3. Verilog I
- Basic synthesizable constructs; synthesis; verification flow

Module 4. Verilog 2
- Synthesizable structures; Common Problems & Fixes; Advanced Examples

Module 5. FSMs
- Types, Coding Style
Module 6. Hierarchy
- Specifying and deciding on hierarchy
Module 7. Complexity
- Datapath & Control; Motion Vector Example; Optimizing Performance and Area; C to Verilog
Module 8. Tricks and Techniques
- Synthesis and code examples for improving design efficiency
- (I might not cover these notes in class - they are more for reference)
- You are free to watch lecture 17 in the recorded lectures
Module 9. Verilog2001
- Brief introduction to features in Verilog 2001 not already covered

Module 10. Verification
- How to verify correctness of modules and system-on-chip
Module 11. Low Power Design
- How to do low-power design in synthesizable code
Module 12. Design For Test
Introduction to how the design is modified to enable manufacturing test
Module 13. Design for FPGAs

Issues specific to FPGAs

Other Links

. ECE 464/520 ASIC Design Spring 2009 Class Notes

If you want a two-up or four-up format (to save paper), you can do this yourself in Adobe Acrobat PDF reader. (From the file menu, select "Print Setup" and click on "properties". The details from that point depend on the version you are running.)

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ECE 464/520 ASIC Design
Spring 2009
Class Notes