Details on how to access EOS computers remotely can be found at : http://www.eos.ncsu.edu/remoteaccess/

You will need to be running Linux, Solaris, or X-win. A copy of X-win32 can be downloaded from http://www.eos.ncsu.edu/software/ .

EOL students wishing to have remote "lab sessions" with the TA, need to install a copy of Elluminate, available at http://distance.ncsu.edu/course_technologies/cms/elluminate.html

Course Advice

Advice on how to structure your MS degree in IC design can be found at www.ece.ncsu.edu/armm

CAD TOOL TIPS

Don't forget the following useful links:

• NCSU specific tool information, including links to documentation , can be found on the NCSU EDA Wiki.
• Sutherland home page , where you can find an on-line version of the reference guide I like to use.  I strongly recommend you have a copy of this reference guide.

Common Verilog Problems

I keep looking at the line with the reported Syntax error and it appears to be OK.

Quite often a syntax error is caused by a missing “;” on the previous line.

I am trying to “pass”  a 2D array e.g. [31:0] Data [0:15] through a module port and it does not seem to be working.

You can't pass (really connect) 2D arrays between modules, only 1D arrays.

I keep getting bugs and HDL warnings that I can't work out.

I'll be blunt.  >95% of these problems are caused by NOT properly following the mantra “design before coding”. 

Common Synopsys Problems

Synopsys tells me that it can not find the .db file specifying the library.  (This usually first occurs in Homework 3).

Review the tutorial.  Make sure to copy the Synopsys setup file into your working directory before running Synopsys.

My synthesis run is taking too long (several hours).

            Make sure that you are not including verify in the compile command, and that you have no embedded SRAMs.  Also review the notes on partitioning in the Hierarchy section.

Synopsys is not synthesizing all the modules, only one of them.

Make sure that you have set current_design = <top module name>, or use the procedure described in the hierarchy notes.

I keep seeing “black boxes” of unsynthesized logic in my final schematic.

These are most likely design ware.  Make sure to run replace_synthetic (as per the provided script) within each module this occurs before running compile. If that does not work use ungroup –flatten –all before running compile