ECE 464/520 ASIC Design
Note: It is my view on homworks is that their main purpose is to prepare you for the project and tests. They are intended as learning experiences and the grade associated with them is mainly for motivation. My policy is that you can collaborate on homeworks but NOT copy solutions, or turn in "group" solutions, or individual copies of "group" solutions. We will look for copied solutions and will use on-line tools for checking copied solutions for Homework 5 and the project. If copying is detected, both of you will be cited for an academic violation. The idea is that you collaborate so you can learn from each other, not distribute the work load. In the project, you do have a partner to help reduce the workload BUT you are not to share code with other groups. Note, some of the points in the project are performance related. I suggest you NOT give away your good ideas.
The tutorials have an FAQ.
-
Homework 1
- Due May 30
- Review of logic basics. If you need a refresher on these topics, there are numerous logic design books in the library, including Wakerley, Katz, etc. etc.
- Should be started immediately
- This Homework is NOT required for students who took ECE 406 in Fall 2010 (except for Question 6).
- Due June 6
- Review of timing notes
- Can be started after completing timing notes
-
Supporting documents:
- Technical Project description
- sram.v
- Article on Aho Corasick
- Project files (zip file )
- Memory files (zip file - save and unzip)
-
Homework 3
- Due: June 13
- Basic design and synthesis
Associated Tutorial and support files found here on the EDA wiki
-
Homework 4
- Due June 20
- More sophisticated Verilog Examples. Make sure to review the tutorial 2 on the wiki .
- Associated Bad FSM Verilog File and Test Fixture
- Can be started after Verilog 2 and, for Q 4, the FSM note
-
Homework 5
- Due July 11
- See tutorial 3 on the eda wiki
- Complex design strategies
- Completes "tool chest" required for project
- Can be started after completing Complexity and Hierarchy notes