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ECE 464/520 ASIC Design

Spring 2011

Class Notes

If you want a two-up or four-up format (to save paper), you can do this yourself in Adobe Acrobat PDF reader. (From the file menu, select "Print Setup" and click on "properties". The details from that point depend on the version you are running.) If specific notes are missing, that means I have not posted them yet.

  • Orientation
  • Module 0. This can only be viewed on-line via the video connection on the home page (lecture 003). This module quickly points out the prior knowledge assumed by this class and goes over timing diagrams and gate level design in more detail. If you felt that HW 1 was easy, you do not need to do watch this class.
  • Problem Sessions. These are review problem sessions in different areas. Timing. Verilog I & II
  • Module 1. Introduction to ASIC Design
    • Moores Law; ASIC Styles; CAD Flows
    • This class has a video supplement reviewing "SC ASIC vs. FGPA" in the media library (This material is supplemental only and introduces no new content)
  • Module 2. Timing
    • Clock Distribution; Flip-flop and latch timing; Timing-aware design
  • Module 3. Verilog I
    • Basic synthesizable constructs; synthesis; verification flow
  • Module 7. Complexity
    • Taught early to assist with project
    • Datapath & Control; Motion Vector Example; Optimizing Performance and Area; C to Verilog\
    • Module 4. Verilog 2
    • Synthesizable structures; Common Problems & Fixes; Advanced Examples