ECE 733 : Digital Circuit Design

Spring 2003

Course Web Page

Instructor : Dr. Paul D. Franzon, paulf_franzon@ncsu.edu

Office Hours : Monday 5-6. Tuesday 5.45 – 6.45 (in DAN 307)

(Note : My regular office is EGRC 443.)

Class Time : Tuesday 4.05 – 5.20, DAN 406

Teaching Assistants

Yawei Jin (yjin3@unity.ncsu.edu) will be maintaining the grade sheets

Ralph Moore (rdmoore@eos.ncsu.edu)

Jian Xu (jxu6@eos.ncsu.edu)

Laboratory Times

Jian Xu : Mon. 6-9pm and Wed. 3-6pm, DAN 253

Ralph Moore : Mon 6:30pm-9:30pm and Wed 8am-11am, DAN 253

Yawei Jin : Tues12:30am-2:30pm, Thurs 9am-1pm in dan253

Laboratory attendance is desirable but not required. Note that little help will be available outside the labs.

Note, you also have remote access to dialup.eos.ncsu.edu and remote.eos.ncsu.edu.

Important Dates

Midterm Exam	March 6	In class
Final Exam	Thursday, May 8	1-4 pm

Syllabus

Lecture Notes

Formats:

1up : one slide per page
2up : 2 slides per page
notes : 1 slide in top 50% of page. Bottom 50% left empty. (My recommendation unless the resolution does not site you)

Introduction in one-up, two-up and notes
CMOS broken into several different sections

Note, this section follows D&P Ch. 4, & Sect. 12.1
Devices (CMOS01) in one-up, two-up and notes formats

At your request here are the update version of cmos1 in one-up, two-up and notes formats
Page 12 updated

Static Circuits (cmos2) in one-up, two-up and notes formats
Dynamic Circuits (cmos3) in one-up, two-up and notes formats
Complete CMOS Notes

Flip-flop papers and notes

Stanford lecture (adopted from Stajanovic)
YuanSvensson89, YuanSvensson97
Partovi, Klass99
Matsui94, StrongArm, Nikolic2000
Stajanovic99
Sakurai, kang2002

Interconnect notes

Interconnect1 in one-up, two-up and notes formats
Interconnect2, set A in one-up, two-up and notes formats
Interconnect2, set B in one-up, two-up and notes formats
Interconnect3, set A in one-up, two-up and notes formats
Interconnect3, set B in one-up, two-up and notes formats

Reliability notes

Reliability in one-up, and two-up formats

Papers

Various Papers can be found in
www.ece.ncsu.edu/asic/ece733/papers/drivers
www.ece.ncsu.edu/asic/ece733/papers/Receivers

§ www.ece.ncsu.edu/asic/ece733/papers/Devices

§ www.ece.ncsu.edu/asic/ece733/papers/LowPower

§ www.ece.ncsu.edu/asic/ece733/papers/RAM

§ www.ece.ncsu.edu/asic/ece733/papers/SOI

§ www.ece.ncsu.edu/asic/ece733/papers/Clock&distnt

Spice Models

We are going to be using some publicly distributed Spice modes for the TSMC 0.18 mm CMOS process for this class.

The CMOS 0.18 mm Spice Models to be used in this class can be downloaded from this MOSIS Site
However, to help you, a full nmos and pmos model spec can be found here
This is the best place to start for this class: http://www.ece.ncsu.edu/asic/ece733/hw/tsmcDeep.sp

Homeworks

§ Homework 1 due Thursday, Feb 27, 2003. Make sure to start it early.

Projects

Project 1 is due Thursday March 20. It is an open-ended design project. I suggest starting early.
Project 2 is due Thursday, April 24.

This project will be rescale so that the discretionary range is from 80 to 120

The W model for differential lines can be found at www.ece.ncsu.edu/asic/ece733/hw/WforDiffTL.doc and www.ece.ncsu.edu/asic/ece733/hw/WforDiffTL.pdf

Miscellaneous Links

On metastability : http://www.deeps.org/Tidbits/meta.html
MOSIS site on 0.18 micron layout rules : http://www.mosis.org/Technical/Layermaps/lm-scmos_scn6m.html
Link to a site with notes for the previous text to this course : http://bwrc.eecs.berkeley.edu/IcBook/slides.htm

Using Hspice & Awaves

Manuals (requires EOS login)

Here is a simple tutorial for Hspice/Awaves:

nedit yourfile.sp &
add hspice
hspice yourfile.sp &
awaves yourfile.sp &