Calendar
| Speaker | Prakash Ramrakhyani |
|---|---|
| Organization | NC State University |
| Location | 136 EGRC |
| Date | September 30, 2002 4:10 PM |
Energy consumption can be reduced by scaling down frequency when peak performance is not needed. A lower frequency permits slower circuits, and hence a lower supply voltage. Energy reduction comes from voltage reduction, a technique called Dynamic Voltage Scaling (DVS).
The useful frequency range of DVS is limited because there is a lower bound on voltage. Lowering frequency permits voltage reduction until the lowest voltage is reached. Beyond that point, lowering frequency further does not save energy because voltage is constant.
We propose Dynamic Pipeline Scaling (DPS), a new technique that reduces energy for frequencies below the DVS frequency range. When frequency is lowered enough, pairs of pipeline stages can be merged to form a shallower pipeline. The shallow pipeline has better instructions-per-cycle (IPC) than the deep pipeline. Since energy also depends on IPC, energy is reduced for a given frequency. A DPS-enabled pipeline has a deep mode for higher frequencies (within the DVS range) and a shallow mode for lower frequencies (below the DVS range). Shallow mode extends the frequency range for which energy reduction is possible. For frequencies below the DVS range, a DPS-enabled deep pipeline consumes from 23% to 40% less energy than a rigid deep pipeline.
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