Calendar
| Speaker | Glenn Rinne |
|---|---|
| Organization | Unitive Inc. and NC State University |
| Location | 136 EGRC |
| Date | October 7, 2002 4:10 PM |
Since the invention of the transistor the ability to interconnect semiconductor devices has lagged the ability to integrate. The cost and delay penalties of off-chip connections have been key drivers in the growth in the number of transistors on a chip, and the motivation for system on a chip (SOC) technologies despite the design, manufacturing, and test challenges such levels of integration present. However, emerging packaging technologies promise improvements in cost and delays that make new partitioning strategies viable.
After a brief historical perspective of packaging and its influence on IC and system design, this presentation will survey the current state of the art in electronic packaging. Then emerging technologies such as chip stacking and laminating will be reviewed with an emphasis on the design opportunities these technologies offer.
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