Calendar

Current Events

3.30

Creating a Sustainable Society

3.16

Sustainable Energy Engineering

2.28

National Science Foundation Day

2.17

Reformulation-Based Approaches to Query Optimization

2.15

FREEDM Day

2.10

WEST: Cloning Data Cache Behavior using Stochastic Traces

2.09

Computer Vision and Image Analysis in the Study of Art

2.08

GSA Social

2.03

Skewed functional processes and their applications

Hardware/Software Codesign of a Real-Time Operating System with an Emphasis on Real-Time Deadlock Detection and Avoidance

Moore's prediction -- commonly known as Moore's "Law" but not a scientific law in the strict sense -- indicates that in the next few years we will have billion-transistor digital circuits (we already have billion+ transistor chips with a large % of DRAM transistors).Clearly, a portion of the billion-transistor integrated circuit market will consist of traditional ASICs, e.g., for super-high volume devices such as cell phones.  Another portion of the billion-transistor integrated circuit market will be dominated by processor designs such as 64-bit x86 architectures from AMD and Intel.The rest of the picture is less clear; however, some percentage will likely be dominated by MultiProcessor System-on-a-Chip (MPSoC) designs with a reasonable (say, 30-60) percent of the chip consisting of reconfigurable and custom digital logic.  One recent example of such an MPSoC is the Virtex-4 FX from Xilinx.

Standard argumentation in favor of RISC indicates that a processor's compiler and architecture must be designed together or codesigned.  Similarly, we will argue that use of an MPSoC can be more efficient with codesign of the architecture and the RTOS to run on the architecture.

Over the past six years, the Hardware/Software Codesign Group at Georgia Tech has worked on some ideas in this domain.  Specifically, this talk will give a brief overview of two of the projects, the System-on-a-Chip Lock Cache (SoCLC) and SoC Dynamic Memory Management Unit (SoCDMMU), with a more detailed review of recently published work in deadlock avoidance using the SoC Deadlock Detection Unit (SoCDDU) and the SoC Deadlock Avoidance Unit (SoCDAU).  For example, the SoCDAU has a specialized hardware structure and associated algorithm which avoids deadlock by two to three orders of magnitude when compared with software algorithms, resulting in a 44% overall speedup in a practical deadlock scenario.

The talk will end with a brief description of a hardware/software RTOS generation framework able to integrate any mix of a variety of hardware RTOS units together with a software RTOS.

Biography:

Vincent J. Mooney III (Member, IEEE and Member, ACM) received the B.S. degree from Yale University in 1991, where he double majored in Electrical Engineering and Computer Science.  He was a member of the 1989 Ivy League Championship football team for Yale and was one of 29 football players to be awarded the NCAA Postgraduate Scholarship upon his graduation in 1991. During the '91 - '92 school year he did research on real-time vision systems at the "Centro de Estudios e Investigaciones Tecnicas" (CEIT) in San Sebastian, Spain.  CEIT is affiliated with the School of Engineering of the University of Navarra.

He received an M.S. degree in E.E. from Stanford University in 1994, an M.A. degree in Philosophy from Stanford in 1997, and the Ph.D. degree in E.E. from Stanford in June of 1998.  He has worked at Bell Labs (Lucent), Allied Signal Aerospace VLSI Design Group, Hughes Network Systems, and Redwood Design Automation (Cadence).  He is currently an Associate Professor in the School of Electrical and Computer Engineering and an Adjunct Associate Professor in the College of Computing, both at the Georgia Institute of Technology in Atlanta, GA.  He is a recipient of the NSF Career Award.

He is Co-Director of the Center for Research in Embedded Systems and Technology (CREST) at Georgia Tech.  He is General Chair of VLSI-SoC 2007 and is an Associate Editor of both ACM TECS and IEEE Transactions on VLSI. His research interests include computer-aided design of integrated circuits with a particular emphasis on hardware-software codesign, reconfigurable computing, real-time operating systems and power-aware architectures and compilers.