Calendar

Current Events

3.30

Creating a Sustainable Society

3.16

Sustainable Energy Engineering

2.28

National Science Foundation Day

2.17

Reformulation-Based Approaches to Query Optimization

2.15

FREEDM Day

2.10

WEST: Cloning Data Cache Behavior using Stochastic Traces

2.09

Computer Vision and Image Analysis in the Study of Art

2.08

GSA Social

2.03

Skewed functional processes and their applications

Flexibly Managing Distributed L2 Caches in Many-Core Processors

Abstract:
Continued technology scaling has opened the era of multicore processors. Multicore processors having two to eight cores are now everywhere (e.g., PCs, servers, and embedded devices), and we will find chips having many more cores in the future. Given many processor cores and various memory components within a single chip, a key question for the next-generation "many-core" processor architects is: How can we utilize the increased amount of on-chip resources (cores, caches, and interconnects) to achieve scalable performance, low power, high availability/yield and dependability? In this talk, not attempting to fully address the question, I will focus on our microarchitecture-OS framework to flexibly manage the available on-chip L2 cache slices. Properly managing the on-chip L2 caches has been shown to be critical for achieving good program performance and low power consumption. In our framework, the OS memory management mechanism is extended to support designating an arbitrary home cache slice for a memory page at run time. The mapping information is efficiently maintained via extending the page table and TLB. The flexible data to L2 cache mapping allowed in our framework can be opportunistically utilized to achieve higher performance and lower power, compared with the two existing hardware-based cache management approaches, namely private caching and shared caching. This work is the first to have the OS take the full responsibility of managing the L2 cache slices on chip.

Biography:
Sangyeun Cho has been an Assistant Professor of Computer Science at the University of Pittsburgh since 2004. Prior to joining Pitt, he worked for Samsung Semiconductor for 5.5 years, where he designed several CalmRISC cores (Samsung's flagship embedded processor cores) and their caches. He was an intern software engineer at MRL, Intel in 1998. He earned a PhD in Computer Science from the University of Minnesota (2002) and a BS in Computer Engineering from Seoul National University, Seoul, Korea (1994). His research interests are in computer architecture, software systems, and their interactions.