Calendar
| Speaker | Srinivas Cheemalapati |
|---|---|
| Organization | IBM |
| Location | EB2, Room 1021 |
| Start Date | October 19, 2007 2:20 PM |
| End Date | October 19, 2007 3:10 PM |
Abstract:
The Cell Broadband Engine (Cell/B.E) processor is a result of the joint effort among the Sony Group, Toshiba and IBM. The primary goal for this architecture is to develop the next generation processor and most importantly address the three challenges facing traditional processors namely memory latency, power and frequency.
Cell/B.E is a multi-core processor with a revolutionary architecture that provides multiple levels of parallelism inside the chip. It falls under the family of heterogeneous microprocessors. It is highly optimized for streaming and media rich applications and suitable for various other workloads in the fields of medical imaging, ray tracing, Monte Carlo simulations to name a few. At a high level, it combines a dual threaded 64 bit PPC core called the PPU and eight synergistic processing units (SPU). The PPU is intended to perform system management and application control functions while the SPUs perform the compute-intensive processing. This allows the data processing and control functions to be decoupled, enabling more application parallelism. The Cell/B.E also defines two storage domains, main and local store and provides Direct Memory Access mechanisms to transfer data to and from the main memory to the local stores in the SPU’s with negligible processor assistance.
With a core frequency of 3.2 GHz and a 204.8 GB/sec very high bandwidth Element Interconnect Bus (EIB) and 25.8GB/sec memory bandwidth, with peak performance numbers of 230 GFlops/sec single precision floating point and about 20 GFlops/sec double precision floating point performance, this is the processor to watch in the area of multi-core processor architectures.
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