supported by:

On-Chip Interconnect

Dr. Paul D. Franzon

paulf@ncsu.edu

919.515.7351, fax. 919.515.2285
www.ece.ncsu.edu/erl/faculty/paulf.html

The goals of this activity are to (1) develop benchmarks for on-chip interconnect structures, and (2) develop design methodologies to improve design convergence in back end CAD tool flows.   This is an ongoing activity in collaboration with Dr. Micheal Steer.   Since item (2) was originated recently, it is not discussed on this page at this point.

For an overview of this activity, please look over this tutorial about on-chip inductance: talk