Paul D. Franzon
Professor of ECE
443 EGRC
paulf@ncsu.edu

919.515.7351, fax. 919.515.2285
www.ece.ncsu.edu/erl/faculty/paulf.html
USPS : ECE, Box 7914, NCSU, Raleigh NC 27695
FedEx : EGRC 419, 2410 Campus Shore Dve., Raleigh NC 27606

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(Last Updated : March 2003)

Curriculum Vitae

Research

The central theme to my research is the design and construction of microsystems and nanosystems.  Within this theme, my group designs and buils VLSI chips, FPGAs, advanced packaging structures, MicroElectroMechanical Systems (MEMS) and employs emerging nanotechnologies.  Many of my projects have an emphasis on interconnect and digital circuits.  Interconnect includes on-chip, off-chip, package and system (including network), mainly electrical and optical.  Digital circuits includes interconnect-related circuits, low-power circuits, and nanoelectronics.  Ongoing themes and current research projects include the following (listed in alphabetical order, click on the link to get access to papers and talks):

A novel scheme for building high-bandwidth, high-density package-level interconnect structures.   Our goals are to build chip I/O and socket and connector structures down to a pin pitch of 75 mm and supporting over 5 Gbps per pin. Activities include package implementation and transceiver circuit design.

Developing hardware architectures to solve point problems in networking.  Recent achievements include faster algorithms for Forwarding Engines that permit TCAM level performance to be achieved with DRAMs.  In the future we intend to look at hardware for network security and applications of reconfigurable computing in this domain (possibly leveraging previous work in configurable computing).

A number of activities revolving around the theme of "system in a package" (SIP) design, including CAD tools, mixed-signal design methods, and key demonstrations.  Future work will include designing and building an "interposer" for RF systems and exploiting circuit techniques to reduce noise in mixed signal designs.

Developing novel structures for micropower digital circuits.  Past work includes memory design.  Current work is focusing on building radio circuits in Silicon-On-Insulator (SOI) technology

Developing tools and methodologies for on-chip interconnect design and characterization.

 We are working with a number of leading scientists on concepts that will turn molecular switches into practical circuits for future digital systems.

We have developed novel structures for (1) Varactors (tunable capacitors) with excellent tuning range, loss characteristics, and linearity, and (2) diffractive mirror arrays.

Infrastructure Items

We also proudly distribute and maintain several important pieces of Infrastructure of use to other Universities and Companies.

This kit supports MOSIS circuit design within the Cadence environment.

This program permits Spice I/O files to be automatically converted to IBIS files.

Graduate Students

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