Chip Package Codesign

Chip Package Codesign

Dr. Paul D. Franzon

919.515.7351, fax. 919.515.2285
www.ece.ncsu.edu/erl/faculty/paulf.html

Brief Description

The goals of this project are to establish the tools and techniques that permit chips and packages to be optimally codesigned together. Projects in this area include:

Spice2Ibis. Development of macromodels, and macromodeling tools for the support of the IBIS I/O CAD standard. For more information on this topic, please refer to http://www.ece.ncsu.edu/erl/erl_software.html#s2ibis3
Optimal chip-package codesign. Methods and examples to improve performance or cost via chip-package codesign. This topic mainly focuses on chip-package codesign leveraging a variety of advanced packaging techniques, including high density substrates, and 3D IC and packaging.

We thank DARPA, NSF and SRC for support of these projects.

Selected Publications:

A.K. Varma, M. Steer, and P.D. Franzon, "Improving Behavioral IO Buffer Modeling Based on IBIS," in IEEE Trans. ADVP, Vol. 31, No. 4, Nov. 2008, pp. 711-721. paper
P. Franzon, Chip-package Codesign, in The Handbook for EDA of Electronic Circuits, L. Scheffer, Luciano Lavagno and Grant Martin (editors), CRC Press, 2005.
J.T. Schaffer, A. Glaser, S. Lipa, and P. Franzon, “Chip Package Codesign of a Triple DES Processor,'' IEEE Trans. Advanced Packaging, 27(1), Feb. 2004, pp. 194-202. paper
P. Mehrotra, P. Franzon, “Optimal Chip Package Codesign for High Performance DSP,” in IEEE Trans. Advanced Packaging, Vol. 28, No. 2, May 2005, pp. 288-297. paper
A.K. Varma, A.W. Glaser, and P.D. Franzon, “CAD Flows for Chip-Package CoVerification,” in IEEE Trans. Advanced Packaging, Vol. 28, No. 1, February 2005, pp. 96-101.
A. Varma, A. Glaser, S. Lipa , M.Steer, P. Franzon, “The development of a macro-modeling tool to develop IBIS models,” Proc. IEEE Electrical Performance of Electronic Packaging, Oct. 2003, pp. 177-280.