Network Hardware Design

Dr. Paul D. Franzon

paulf@ncsu.edu

919.515.7351, fax. 919.515.2285
www.ece.ncsu.edu/erl/faculty/paulf.html

Brief Description

The goals of this project are to determine efficient hardware algorithms and architectures that solve specific problems in networking. Problem areas being addressed include filters, correlators, routing, etc. Target applications include network security, classification, and better hardware support for advanced network services.

Selected Publications:

· M. Yadav, A. Venkatachaliah, P.D. Franzon, “Hardware Architecture of a Parallel Pattern Matching Engine,” in Proc. ISCAS 2007, pp. 1369-1372. paper

· M. Yadav, P. Hamilton, R. Sears, Y. Viniotis, T. Conte, P.D. Franzon, “A configurable classification engine for polymorphous chip architecture,” ACM BEACON Workshop, Boston, OCT. 2004.

· M. Aldwairi, T. Conte, P. Franzon, “Configureable string matching hardware for speeding up intrusion detection,” Computer Architecture News 33(1), pp. 99-107.

· P. Mehrotra, P.D. Franzon, “Novel architecture for fast address lookups,” IEEE Communications Magazine, 40(11), November 2002, pp. 66-71. paper