On Chip Interconnect

Dr. Paul D. Franzon

paulf@ncsu.edu

919.515.7351, fax. 919.515.2285
www.ece.ncsu.edu/erl/faculty/paulf.html

Brief Description

This long standing set of projects has focused on better understanding on-chip interconnect and developing new solutions to on-chip interconnect problems. Recent achievements include the following:

· Investigation of how to best redesign chip sets to take maximum advantage of 3DIC / TSV technologies (please see 3DIC project for details)

· Development low-power on-chip equalization schemes to compensate for high frequency effects

· Development of 22 nm pitch routable nano-wires (See nanointerconnect project for details)

· Development of on-chip frequency domain measurement techniques

We gratefully acknowledge the support of DARPA, NSF and SRC in this work.

Selected Publications

• L. Zhang, J.M. Wilson, R. Bashirullah, L. Luo, J. Xu and P. Franzon, "A 32-Gbps On-Chip Bus with Driver Pre-Emphasis Signaling," in TVLSI, Vol. 17, No. 9, Sept. 2009, pp. 1267-1274. paper
•  L. Zhang, J.M. Wilson, R. Bashirullah, L. Luo, J. Xu, P.D. Franzon, “Voltage-Mode Driver Pre-emphasis technique for on-chip global buses,” in IEEE Trans. VLSI, Vol. 15, No. 2, Feb. 2007, pp. 231-236. paper
• Baribrata Biswas, Allen Glasser, Steven Lipa, Michael Steer, Paul Franzon, Dieter Griffis, Phillip Russell, “Experimental Electrical Characterization of On-Chip Interconnects'', IEEE Topical Meeting on Electrical Performance of Electronic Packaging , Oct. 1997, pp. 57-59.

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