This thesis describes circuit techniques for precise manipulation of digital waveforms. This manipulation is in the form of either a phase-adjustment (i.e., delay) of an input waveform or generation of a waveform from a predefined bit pattern. Using relatively coarse delay elements, these vernier techniques allow very fine control of the placement of edges in output waveforms. Two significant advantages of the vernier techniques are that high-precision operation is obtainable using standard (inexpensive) CMOS technology and implementations can be realized with simple architectures.
Two techniques for creating high-precision delays are described. The two delay vernier technique uses the relationship between two coarse but precisely controlled delay elements to generate a high-resolution delay. The one delay vernier technique achieves precise edge delay control using the relationship between a single coarse delay and the period of the waveform. Test chips were fabricated with implementations of each of these techniques. The two delay technique achieved a delay resolution of 50ps in 2um CMOS, while the one delay technique achieved a delay resolution of 50ps in a 0.8um CMOS process. Practical issues that affect the implementations, as well as the design and detailed results of the test chips, are examined.
In addition to creating precise delays for digital waveforms, the vernier techniques are also applicable to digital pattern generation. The vernier technique for pattern generation uses the difference between two coarse delays to control the precision with which edges can be placed in a generated digital waveform. An additional advantage of this technique is that high-speed patterns can be created using relatively low-speed clocks. This technique has been implemented in a 1.2um CMOS test chip, which can place edges in a generated pattern with 100ps resolution at a data rate of 667Mb/s. The design and testing results of this chip are discussed.
The precision of the vernier techniques is limited by how well the coarse delays can be controlled over process and environmental variations. Maximizing performance of the vernier systems requires methods for automatically maintaining the delay values. This work describes some control circuits that are useful in setting and maintaining delays. These controls were implemented in the test chips mentioned above, and the effect of their operation on system performance is examined.