Abstract:
Skewed-clock optimization is a clock scheduling technique used in digital systems to improve system performance. Using this technique, the clocking of storage elements are no longer synchronized at a specific time instant. By adjusting the clocking times (scheduled skew) of storage elements, combinational logic with longer delays can have more cycle time to propagate. Thus system cycle time and latency can be reduced.
There are two important issues in developing this optimization technique. The first is how to choose appropriate skews to improve system performance. The second is how to distribute reliable skewed clocks in the presence of manufacturing and environmental variations. Without careful choosing of clocking times and control of unintentional skews, system performance might be degraded instead of improved.
A theoretical framework is presented for solving the first problem for optimally scheduling skews. %minimizing the cost function, system cycle time or latency, subject to a set of linear constraints. The solution of this optimization problem can be obtained either by the simplex algorithm, whose time complexity is exponential in the worst case, or by an efficient polynomial-time algorithm based on the Bellmann-Ford algorithm. This framework can handle edge-triggered flip-flop based designs, transparent latch based designs, or mixed ones.
Generally, the skewed-clock optimization problem has no restrictions on the values of scheduled skews in the optimization process. %allows designers to choose arbitrary values of skews in the optimization process. However, many practical issues prevent designers from using arbitrary scheduled skews. One of the issues is the difficulty in creating and distributing arbitrary skews, and thus scheduled skews can only be chosen from a set of predetermined values. Another issue is the design cost and time, which can be greatly reduced if only the storage elements along the critical paths, instead of every storage element, are speeded up with scheduled skews. This type of optimization problem is called constrained skew optimization and is also discussed in the thesis. Efficient algorithms are presented for solving this problem.
Retiming is another timing optimization technique for maximizing speed of operation by relocating storage elements, while resynchronization allows optimal insertion of storage elements to improve system performance. Combined with skewed-clock optimization, these two techniques give designers additional ways to maximize system performance. Thus our theoretical framework allows concurrent optimizations including retiming and resynchronization.
After scheduling a set of skews, it is natural to ask how to deliver them. In delivering skewed clocks for high-speed digital systems, the primary challenge is to minimize unintentional skews. In practice, process and temperature variations, line loading, and supply voltage changes can cause delays along the clock tree to range from 0.4 to 1.4 times their nominal values. Therefore, it is unreliable to deliver skewed clocks with either a passive clock tree or an active buffer tree. In the thesis, a self-calibrating clocking distribution scheme is provided which generates multi-phase clocks based on a reference clock. In order to minimize unintentional skews, the scheme dynamically adjusts its phase across manufacturing and environmental variations. This tracking process is implemented with an all-digital pseudo phase-locked loop. It is theoretically shown that the absolute value of unintentional skews, originating from the quantization error, is limited to (Ds+Dp), where Ds and Dp are the sampling and phase resolutions, respectively. Consequently, reliable clocking for a skewed-clock design can be achieved. This tracking scheme has been verified through the implementation of a demonstration chip. Testing results are consistent with the theoretical proof and show that unintentional skews can be well controlled with such a scheme.