This dissertation first presents a scheme and circuitry for demultiplexing and synchronizing high-speed serial data using the matched delay sampling technique. By simultaneously propagating data and clock signals through two different delay chains, the sampler achieves a very fine sampling resolution which is determined by the difference between the data and clock delays. Thus, the sampler is capable of oversampling high speed data signals without the need of a high-speed clock and it can be used in a data recovery circuit. A data recovery circuit using the matched delay sampling technique has been designed and fabricated in 1.2um CMOS technology. The chip has been tested at 417Mb/s (2.4ns NRZ) input data. To overcome the speed limitation by I/O pads, the recovered data is demultiplexed into four 104Mb/s output streams with 800mW power consumption at 4V power supply. While recovering data, the sampling clock running at 1/4 of the data frequency is phase-tracked with the input data based on the information extracted from a digital phase control circuit. Based on z-transform, criterion for the system stability is derived accordingly.
A Markov chain model is developed to obtain the optimum oversampling number per one bit datum in the oversampling data receivers. The model is able to predict the input signal-to-noise ratio versus bit error rate (BER) of the data recovery system for various oversampling ratios. The more number of samples per single bit results in the better performance on BER at the same input SNR. To achieve 10-11 BER, eight times oversampling has about 2dB input signal penalty compared to 16 times oversampling. In the oversampling data recovery circuit, the recovered clock can be updated either in each data bit or in every multiple bits. Two different clock update schemes were analyzed and compared. The single bit recovered clock updating scheme has about 1.5dB penalty against the multiple bits (four bits) clock updating scheme if 16 times oversampling is used.