Recent Publications

Books and Book Chapters:
1. Cavin, and Liu, Emerging Technologies: Designing Low Power Digital Systems, ISBN-0-7803-3328-4, IEEE Press, May, 1996.
2. Gray, Liu, and Cavin, Wave Pipelining: Theory and CMOS Implementations, ISBN-0-7923-9398-8, Kluwer Academic Publishers, 1994.
3. C. Gray, W. Liu, and R. Cavin, "Timing Constraints for Wave Pipelined Systems," in Clock Distribution Networks in VLSI Circuits and Systems, (edited by E. Friedman), pp. 170-187, IEEE Press, ISBN-0-7803-1058-6, May 1995.
4. W. Liu, R. Cavin, T. Schaffer, G. Moyer, M. Clements, J. Kang, J. Medero, and H. Hsieh, "Matched Delay Technique for High-Speed Digital Design," in Low-Power High Frequency Microelectronics, Chapter 16, IEE, 1996, ISBN-0-85296-874-4.
Papers:
1. W. Burleson, M. Ciesielski, F. Klass, and W. Liu, "Wave-Pipelining: A Tutorial and Research Survey", IEEE Trans. on VLSI vol.6, no. 3, pp. 464-474, Spetember, 1998
2. H. Hsieh, W. Liu, P. Franzon, and R. Cavin, "Clocking Optimization and Distribution in Digital Systems with Scheduled Skews," Journal of VLSI Signal Processing 16, pp. 131-147, 1997.
3. J. Kang, W. Liu, and R. Cavin, "A CMOS High Speed Data Recovery Circuit Using the Matched Delay Sampling Technique," IEEE Journal of Solid-State Circuits, vol. 32, no. 10, pp. 1588-1596, 1997.
4. G. Moyer, S. M. Clements, W. Liu, J. T. Schaffer, and R. Cavin, "The Delay Vernier Pattern Generation Technique," IEEE Journal of Solid-State Circuits, vol. 32, no. 4, pp. 551-562, 1997.
5. G. Moyer, S. M. Clements, W. Liu, J. T. Schaffer, and R. Cavin, "A Technique for High-Speed Fine Resolution Pattern Generation and its CMOS Implementation," 16th MIT Conference on Advanced Research in VLSI, pp. 131- 145, March. 1995.
6. W. Liu, R. Cavin, T. Schaffer, G. Moyer, M. Clements, J. Kang, J. Medero, and H. Hsieh, "Matched Delay Technique for High-Speed Digital Design," in Low-Power High Frequency Microelectronics, Chapter 16, IEE, 1996, ISBN-0-85296-874-4.
7. G. Moyer, S. M. Clements, W. Liu, "Precise Delay Generation using the Vernier technique," Electronics Letter, pp. 1658-1659, Vol. 32, No. 18, 1996.
8. S. M. Clements, W. Liu, J. Kang, R. Cavin, "Very High Speed Continuous Sampling Using Matched Delay," Electronic Letters, vol.30, no. 6, pp. 463-464, March 1994.
9. H. Hsieh, W. Liu, and R. Cavin, "Concurrent Timing Optimization of Latch-Based Digital Systems," ICCD95, pp. 680 - 685, Oct. 1995.
10. W. Liu, C. Gray, D. F an, W. Farlow, T. Hughes, and R. Cavin "A 250-MHz Wave Pipelined Adder in 2-um CMOS," IEEE Journal of Solid-State Circuits, vol. 29, no. 9, pp. 1117-1128, September 1994.
11. C. T. Gray, W. Liu, and R. Cavin, "Timing Constraints for Wave-Pipelined Systems," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 13, no. 8, pp. 987-1004, August 1994.
12. C. T. Gray, W. Liu, and R. Cavin, "Circuit Delay Calculation Considering Data Dependent Delays," Integration: the Journal of VLSI, vol. 17, pp. 1-23, August 1994.
13. C. Gray, W. van Noije, W. Liu, T. Hughes, R. Cavin, "A Sampling Technique and its CMOS Implementation with 1 GBit/s Bandwidth and 25 ps Resolution," IEEE Journal of Solid-State Circuits , vol. 29, no. 3, pp. 340-349, March 1994.
14. W. van Noije, J. Navarro, W. Liu, "Precise Final State Determination of Mismatched CMOS Latches," IEEE Journal of Solid-State Circuits, vol. 30, no. 5, pp. 607-611, 1994.
Supervised Dissertations;
1. G. Moyer The Vernier Techniques for Precise Delay Generation and Other Applications, PhD Thesis, North Carolina State University, 1996.
2. J. Kang CMOS High Speed Data Recovery Circuit Design using Matched Delay Sampling Technique , PhD Thesis, North Carolina State University, 1996.
3. H. Hsieh, Clocking Optimizationn and Distribution in Digital Systems with Scheduled Skews, PhD Thesis, North Carolina State University, 1996.
4. C. T. Gray, Optimal Clocking of Wave Pipelined Systems and CMOS Applications , PhD Thesis, North Carolina State University, 1996.