Wave Pipelining

Technical Papers:
1. W. Liu, C. Gray, D. F an, W. Farlow, T. Hughes, and R. Cavin "A 250-MHz Wave Pipelined Adder in 2-um CMOS," IEEE Journal of Solid-State Circuits, vol. 29, no. 9, pp. 1117-1128, September 1994.
2. C. T. Gray, W. Liu, and R. Cavin, "Timing Constraints for Wave-Pipelined Systems," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 13, no. 8, pp. 987-1004, August 1994.
3. C. T. Gray, W. Liu, and R. Cavin, "Circuit Delay Calculation Considering Data Dependent Delays," Integration: the Journal of VLSI, vol. 17, pp. 1-23, August 1994.
4. C. Gray, W. van Noije, W. Liu, T. Hughes, R. Cavin, "A Sampling Technique and its CMOS Implementation with 1 GBit/s Bandwidth and 25 ps Resolution," IEEE Journal of Solid-State Circuits , vol. 29, no. 3, pp. 340-349, March 1994.
5. W. van Noije, J. Navarro, W. Liu, "Precise Final State Determination of Mismatched CMOS Latches," IEEE Journal of Solid-State Circuits, vol. 30, no. 5, pp. 607-611, 1994.
Book:
1. Wave Pipelining: Theory and CMOS Implementation , Kluwer Academic Publishers, 1994, ISBN 0-7923-9398-8.
Theses:
1. Optimal Clocking of Wave Pipelined Systems and CMOS Applications , PhD Thesis, North Carolina State University, 1996.