| Sample .s2i file | | HSPICE Model obtained from | http://www.micron.com/products/partdetail?part=MT48LC32M16A2TG-75%20IT | 512Mb SDRAM Component : MT48LC32M16A2TG-75 IT. | | Specify the IBIS version and file revision number. | [IBIS Ver] 2.1 [File rev] 0.1 [date] Sept 15 2006 [source] NCSU conversion of Micron HSPICE model |[Iterate] [Spice type] hspice [cleanup] | Now specify some global parameters. These parameters will apply to | _all_ the models in this file. | | Note on the [Temperature range] keyword: Since this is a CMOS circuit, | the min column contains the highest temperature, since this temperature | causes or amplifies the "min" (slow, weak) behavior, while the max | column contains the lowest temperature, since this temperature causes or | amplifies the "max" (fast, strong) behavior. If this were a bipolar | circuit, these temperature values would be reversed. | [temperature range] 40 85 0 [voltage range] 3.3 3.0 3.6 [sim time] 1.5ns [vil] 0 0 0 [vih] 1 1 1 [Tr] 100ps 100ps 100ps [Tf] 100ps 100ps 100ps [rload] 50 | | Specify the default pin parasitics | typ min max [R_pkg] 195.2m 155.4m 250.3m [L_pkg] 4.03nH 2.88nH 5.00nH [C_pkg] 1.03pF 0.83pF 1.19pF | | Component Description | [Component] MT48LC32M16A2TG-75 IT [Manufacturer] Micron Technology | | Specify the SPICE file where the circuit is located. | [Spice file] y27b_dq.sp | | Now specify the pin list. Since we're just creating an IBIS file for | the driver, we'll use a very short pin list. | | The pin list formats can be found in doc/s2ibis2.txt. Briefly, the | first line of each pin is of the form | | pin_name spice_node signal_name model_name | | If a pin description has more than one line (e.g. the first pin in the | pin list below), the second line is of the form | | -> input_pin enable_pin | | Note that the second line must begin with the symbol "->". | | Therefore, a "translation" of the pin list below would read: | | - The first pin is pin number "out". It corresponds to node "out" in | the given SPICE file. The signal carried on this pin is named | "out". This pin is represented by the model "tristate_driver"; | it is driven by pin number "in" and is enabled by pin number | "enable". | - The second pin is pin number "in", which corresponds to node "in" | in the SPICE file; its signal is named "in". The model for this | pin is "dummy". | - The third pin is pin number "enable", which corresponds to node | "enable" in the SPICE file; its signal is named "enable". The | model for this pin is "dummy" (the same model as the input pin). | - The fourth pin is pin number "gnd", which corresponds to node "gnd" | in the SPICE file; it carries the "gnd" signal. The model for this | pin is "GND", which is an s2ibis2 reserved word that denotes a | ground supply pin. | - The fifth pin is pin number "vdd", which corresponds to node "vdd" | in the SPICE file; it carries the "vdd" signal. The model for this | pin is "POWER", which is an s2ibis3 reserved word that denotes a | power supply pin. [Pin] DQ pad DQ DQBUFF_FULL -> in ena in in in dummy ena ena ena dummy vssq vssq vssq GND vccq vccq vccq POWER [Model] DQBUFF_FULL [Model type] I/O [Polarity] Non-inverting [Enable] Active-High [Model file] micron_y27b_typ.mod micron_y27b_min.mod micron_y27b_max.mod [vinl] 0.99 [vinh] 1.61 [Vmeas] 1.3 [Rref] 50 [Vref] 1.3 [Cref] 30p | typ min max [C_comp] 1.1pf 1.1pf 1.1pf | [Model Spec] | Subparam typ min max | Vinh 0.950 0.900 1.000 | From JEDEC specs + VDDQ/2 voltage | Vinl 0.550 0.500 0.600 | From JEDEC specs + VDDQ/2 voltage | Vmeas 0.750 0.700 0.800 | VDDQ/2 voltage | [Rising waveform] 50 0 0 0 NA NA NA NA NA [Rising waveform] 50 2.6 2.5 2.7 NA NA NA NA NA [Falling waveform] 50 0 0 0 NA NA NA NA NA [Falling waveform] 50 2.6 2.5 2.7 NA NA NA NA NA | | Now specify stuff for the model "dummy". Since we only wanted to model | the driver, we use the [NoModel] switch to tell s2ibis2 not to create | this model. | [Model] dummy [NoModel]