Current Research
 
 

Motivation for the research begin from the need for circuits and gates from these NDR devices.  A majority of the team's effort has been focused on developing a logic family using this molecular devices.  From this family, more complex circuits will be constructed using the circuit gates as building blocks.

To create an accurate model of the NDR devices for circuit simulation purposes, data collected by Jia Chen at Yale was used to construct an HSPICE element.  The IV curve, as measured by Jia Chen, is shown to the left.  The peak-to-valley current shows a 1000X on/off ratio.  The current peak for this particular device occurs at 2.12 volts, however that value can vary from device to device.

By loading the diode with a resistor, two stable operating points can be identified.  This is illustrated in the load line diagram shown in the figure below and to the right.  By adjusting the value of the load resistor, the slope of the load line can be adjusted thereby affecting the separation of the high/low voltages.  This work was inspired from previous research performed by J. Huber et. at., published in the IEEE Trans. Electron. Devices 44, 2149 (1997).  As this time, AND, OR and INVERTER structures are being designed and simulated.  From these structures, simulations of more complex logic blocks and interconnect strategies are under investigation.
 
 

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