NC State University

ASIC Design Tutorial

The purpose of this tutorial is to familiarize you with the following tools and methodologies:

Behavioral (RTL-level) simulation using the Cadence Verilog-XL and Cadence Cwaves waveform viewer in `stand-alone' mode. This section also discusses how to use the Cadence Verilog-XL simulator without a waveform viewer (i.e. in text I/O format).

How to synthesize a simple design using a script through Synopsys using design_analyzer. The script demonstrates correct use of the 0.8u CMOSX standard cell library as installed at NCSU.

How to synthesize a simple design using a script through Synopsys using dc_shell. The script also demonstrates correct use of the 0.8u CMOSX standard cell library as installed at NCSU.

Introduce you to post-synthesis verification using Verilog-XL. This can be achieved by running the script simrun.

Where to find answers. This section discribes how to find information about Cadence, Synopsys and other resources local to NCSU.

Simulation using stand alone Verilog and Cwaves

The purpose of this section of the tutorial is to familiarize you with simulation of an RTL description using stand-alone Verilog and Cwaves. We will also show how simulation output can also be obtained through a plain text interface. This can be done strictly through textural (TTY) interfaces.

At Eos prompt type the following:

mkdir ~/ece520
add ece520_info
add cadence 

//if a .cdsinit already exists in home directory rm ~/.cdsinit and rm ~/.synopsys_ds.setup

cp /ncsu/ece520_info/tools/.cdsinit ~/
cp /ncsu/ece520_info/tools/.synopsys_dc.setup ~/

Note: You may have to restart your environment session since you updated your .cdsinit and .synopsys_dc.setup. The simplest way to do this is to log out and log back in. If this is the case add ece520_info and add cadence (like you did above) upon restart of session.

cp /ncsu/ece520_info/tools/simrun ~/ece520
cp /ncsu/ece520_info/tools/count*.* ~/ece520
cp /ncsu/ece520_info/tools/test.v ~/ece520
cd ~/ece520 

Now simulate the design and test fixture together by entering the command:

verilog count+test.v

Then open the file count+test.v with your favorite ASCII text editor:

Things to notice about count+test.v:

  • It contains two modules -- the module being built counter, and a test_fixture.
  • The $display command prints simulation results. If you want to print several messages on a single line you should use the $write task.
    Ex. $display("HELLO WORLD");
    $display("input = %h",input);  
  • The $monitor task provides the ability to monitor and display the values of any variables or expressions specified in exactly the same manner as for the $display system task-including the use of escape sequences for special characters and format specifications.
    Ex. $monitor("time %t:clock %b:in %h:zero %b",$time,clock,in,zero);
  • The $shm_open("all.shm"); command saves all waveforms in a database so that you will be able to view them in cwaves.
    Ex. $shm_open("waves.shm");
  • The $finish command is used to end the simulation.

then insert the following line into count+test.v after the $shm_probe("AS"); line in count+test.v:

$monitor("time %t:clock %b:in %h:zero %b",$time,clock,in,zero);

save the count+test.v file and then retype the command at the Eos prompt:

verilog count+test.v

You will now notice that you have essentially added a probe that monitors the signals zero, time, clock, and in. You will then see textural output appear on the screen that looks like:

Verilog Text Output

 

CWAVES:

You can also view waveforms from a tool called cwaves. Note: This is a GUI tool and you won't be able to run this in a TTY session such as telnet. To start cwaves you now type:

cwaves &

This starts cwaves and allows you to view the database file that you have created using $shm_open command in the test-fixture.

From the menu pulldown in cwaves:

click on File
select Load Data from the pulldown menu
click on ok
click on Edit

select Browser/Display tool
click on the subscope test_fixture
click on the down arrow
(right above test_fixture)

add all the signals(in[3:0],clock,dec,latch,zero) by clicking on the signal and then clicking on the Add Selections button

Your screen should look like this after adding the signals in the Browser/Display Tool window:

cwaves Browser/Display Tool Settings

 

then to close the Browser/Display window  

click on the cancel button

You will now see the signals waveforms that you have selected.

You can view the waveforms as a whole by

selecting view
selecting zoom fit
 

(Also, you could have selected the button on the left that looks like a magnifying glass with a equal's sign)

And finally you will have the waveforms of all your signals that you have selected!

cwaves waveform

Another useful feature in cwaves is to execute the `save setup' command.

Find this command in the pull down menus before exiting cwaves.

After you have saved a setup, you can restore it in subsequent sessions and avoid having to go through the Browser steps.

Synthesis using script(design_analyzer)

In order to synthesize your design you use a tool called design_analyzer at the Eos prompt type:

add synopsys
design_analyzer &
 

(Note: design_analyzer is an X application you will not be able to run this application from a telnet session or TTY session)
This will bring up the Synopsys Design Analyzer 

click on Setup
select Command Window
 

at the bottom of the design_analyzer you can enter end commands and run synthesis scripts.

type at the design_analyzer prompt: include count.sc

This loads the count.sc synthesis script and executes the commands in the synthesis script.

A few notes about the script that you just ran:

  • link_library = {"ms080cmosxCells_XXW.db"} //This links in the cmosx worst library to and is used to check for setup timing violations.
  • link_library = {"ms080cmosxCells_XXB.db"} //This links in the cmosx best library and is used to check hold time violations.
  • You will need to check for both in your synthesis script in order to meeting timing requirements.
  • When you change one portion of your design to meet setup/hold time violations you need to check for the other.

To view/plot your design:

  1. click on the counter(actually the box just above the text)
  2. click on the down arrow on the left side of the window
  3. click on the and gate on the left side of the window

 

This will give you a gatelevel/schematic display of your design:

gatelevel/schematic display

Now you can plot your design by:

  1. select file
  2. click on plot
  3. select your plot options 

Note how when you use the graphical interface, the equivalent script commands appears in the command window. If you want, you can add these to your script for use in future synthesis runs.

Synthesis using a script (dc_shell)

For those that want to run synthesis using from the command line (and via TTY) there is a way to do it through Synopsys: dc_shell. The way you would execute the synthesis script count.sc using dc_shell would be:

add synopsys
dc_shell -f count.sc
 

To view/plot your design add the following lines to your synthesis script after the write -f verilog -o count_final.v line:

create_schematic -size infinite -gen_database
create_schematic -size infinite -symbol_view
create_schematic -size infinite -hier_view
create_schematic -size infinite -schematic_view
plot_command = "cat >plot.ps"
plot -hierarchy

Note: The plot_command line above actually generated a postscript file called plot.ps

Post-synthesis verification (simrun) +typdelay

To do post-layout verification you can run the script simrun. At the Eos prompt type  

simrun

Open the simrun script in your favorite text editor. Note the following features:

  • The general format of the Verilog command line is
    verilog +???delay <verilog file list>
  • Here, we are using typdelay so we can obtain a rudimentary verification of timing. Later, we will show you how to use SDF (standard delayformat) interfaces to conduct a more accurate timing verification.

Where to find answers

There are various ways of getting information about the cadence environment and problems that are associated with cadence and synopsys. You should check the newsgroups ncsu.cadence and ncsu.synopsys from time to time to post questions and look for answers to problems that you are having.

You can also find Cadence and Verilog-XL documentation by running

openbook &

And synopsys documentation is at

iview &

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