First Encounter "Counter" Tutorial

You need to create a directory and copy necessary files into your that directory. These files are located in /afs/eos/lockers/research/ece/wdavis/temp/. Type the following command to get all the files ready.

	mkdir cadence		
	cd cadence
	mkdir tutorial
	cd tutorial
	copy -r /afs/eos/lockers/research/ece/wdavis/temp/cellsLib .
	copy -r /afs/eos/lockers/research/ece/wdavis/temp/ios .
	copy -r /afs/eos/lockers/research/ece/wdavis/temp/TSMC025_deep .
	copy /afs/eos/lockers/research/ece/wdavis/temp/count_hierarchy.v
	copy /afs/eos/lockers/research/ece/wdavis/temp/ncsulib25.lef .
	copy /afs/eos/lockers/research/ece/wdavis/temp/ncsulib25.tech .
	copy /afs/eos/lockers/research/ece/wdavis/temp/count.cts.auto .
	copy /afs/eos/lockers/research/ece/wdavis/temp/counte.tc .
	copy /afs/eos/lockers/research/ece/wdavis/temp/counte.conf .
	add cadence
	encounter
	

Now you are ready to run your 1st First Encounter tutorial. Remember you'd better run encounter in the front end mode so that you can see the information that was printed on the screen when you are running FE.

General Bind Keys

Key	Action	Description
q	Attribute	Display the object attribute form on selected object.
f	Fit Display	Zooms the display to fit the design area.
g	Group	Moves up the hierarchy on the highlighted Hinstance.
u	Ungroup	Moves down the hierarchy on the highlighted Hinstance.
v	View DB	View the attributes of highlighted object.
z	Zoom-in	Zooms in the display, 2x.
Z	Zoom-out	Zooms out the display, 2x.
Shift	Select	Allows multiple selections of objects.
Arrows	Pan	Pans the display in direction of arrow.
Delete	Ruler	Removes last ruler displayed.
Space Bar	Focus	Changes the focus of overlapping objects

Auto Query Bind Keys

Key	Action	Description
n	Focus	Changes the focus of overlapping objects.
p	Focus	Changes the focus of previous overlapping object.

Edit Special Route form Bind Keys

Key + Mouse Button	Action	Description
Shift + Left button	End	Ends the drawing mode for creating special route.
Delete	Delete	Removes last point/segment.
Arrows	Moves	Moves the current segment in direction of arrow.
W	Warp	Allows drawing pencil to move freely.

Steps

1. Testcase Information:
   The testcase is a counter synthesized with our ncsulib25 library. The netlist format is hierarchical Verilog, and the process is 5 layers of metal. It has one clock source, clock.
2. Design Import:
   Open the Design Import form (Design → Design Import...) and complete the Design form as shown below. Remember that you can use the file widget to enter a single file name but you must type in the directory names. Next, click the Power tab and enter

   vdd

   in the Power Nets text box and

   gnd

   in the Ground Nets text box, as shown below. Next, click the Power/Ground Connection bottom and enter

   vdd

   in the Pins text box and in the To Global Net text box, as shown below. Click add to list and then change

   vdd

   to

   gnd

   , click add to list again. Then click close. Click the Ok button to import the design. If you want, you can click the Load button. Select

   count.conf

   to set up the form's configuration to import the design and click the Open button to load the form. Click the Ok button to import the design. It does the same thing what you did just now.
3. Specifying chip size:
   Open the FloorPlan → Specify Floor Plan form and use the default setting for Core Size by: Aspect Ratio:. Next, under the selection of Core Margins by: Core to IO Boundary, enter 100 for Core to Left, Core to Right, Core to Top, and Core to Bottom. Click OK to move the IO pads 5 Microns from the outside edge of the core box and this sets the IO box. Now the die box size is set by the height of the IO pad instances.
4. Design Browser:
   Open the Utility → Design Browser... to view the design that was imported.
5. Add power rings:
   FloorPlan → Power Planning → Add Rings... Fill in what is showed in the figure below. Fill in 1.5 in the width text box and 1 in spacing text box.You can save your floorplan by open floorplan→save Floorplan→FP
6. Run Amoeba Placement
   Open the Place → Place... form. Now, click the Ok button (use the default Medium Effort.)
7. Viewing the Design after Placement
   Once the placement program is done, you can view the placed design in the Placement view you will see some small blocks (our standard cells) are placed in the core area you created just now.
8. Run Clock Tree Synthesis
   Open the Clock → Synthesis Clock Tree form and select the clock specification file, count.cts.auto. DO NOT select Display Clock Tree form item. Click Ok to run synthesis. You will see that some buffers are added into the design after you run clock tree synthesis.Now open Clock → Display Clock Tree select Display Clock Tree and click OK, see what will happen.
9. Connect power and ground
   Open route→Connect to global net. Fill in exactly what is show in the following picture. Click apply. Then change vss to vdd and clock apply again.
10. Run Trial Route
    Open the Route → Trial Route... form. Click the Ok button when ready. No option is to be selected. Or instead, you can type the First Encounter (FE) command,

    trialRoute

    , in the SPC console window to run Trial Route.
11. Save the Design
    It is a good idea at this point to save everything you have done in the First Encounter tool. Open the Design → Save Design... form. Enter your own archive file name or use the default and click the Save button when ready. Now you can restore your work in a future First Encounter session. Note that no netlist file is saved unless the imported design was changed by First Encounter.
12. Setting Timing Models
    In the timing library that was read in during design import, there are temperature, process, and voltage conditions that are modeled. Open the Timing → Specify Operating Condition form and click OK
13. Extract RC Data
    To extract the capacitance for the design, open the Timing → Extract RC form. Since it will take time to generate and write files over the network, select formats of interests and generate the simulation files. The files are written to your work directory. Now, you can examine them.
14. Generate Wire Load Model
    To generate the wire load models at every level of the hierarchy, open the Timing → Generate Wireload Model form. Select Cell or Instance Based and click the Ok button. There are 4 wireload files created in your work directory, 2 data files Count_SP.wl.hier and Count_SP.wl.flatand 2 load script files Count_SP.wl.hier.scr and Count_SP.wl.flat.scr.
15. Calculate Delay
    Next, delays are calculated for the interconnect wires and include instance delays. To do this, open the Timing → Calculation Delay... form. To see what delay default is used for large nets, open the Design → Design Import's Timing & Power Defaults page. Select the Ideal Clock option if you did not run clock tree synthesis or deselect it if you did run clock tree synthesis. Click Ok when ready. A file in SDF format is created.
16. Run Timing Analysis and Generate Slack Report
    Open the Timing → Timing Analysis form and run the default Setup Time Analysis by clicking OK. When done, view the slack report by using the Timing → Slack Brower... to open the slack report file,

    Count_SP.slk

    .

Congratulations, you have finished your first time encounter tutorial!