NC State University

ECE 741: Sequential Machines

Homework #1 - Spring 2003Assignment

Design and synthesize a simple Verilog Module using Synopsys Design Compiler and the standard-cell library provided below. VHDL or Module Compiler are allowed if you prefer. Your design should contain between 200 and 1000 cells and include a simple testbench to demonstrate its functionality. Reuse of designs from previous classes is allowed and encouraged. In addition, your design should include estimates of area, delay, power, and CAD tool execution statistics.

Tutorial

The following is a brief tutorial with example files to illustrate what is expected for this assignment.

  1. Source the MUSE setup script with the following command:
    source /afs/eos.ncsu.edu/lockers/research/ece/wdavis/setup/muse_setup.csh
    This script sets the MUSE_HOME environment variable and extends your path to include some helpful utilities.
  2. Create a run directory for this assignment and copy the following files into this directory:
    • addreg_behav.v - Behavioral RTL code for a 3-bit adder followed by a register
    • tb.v - Test-bench for the addreg module
    • hw1_sim.csh - Script for executing a Verilog Simulation
    • hw1_syn.csh - Script for Synthesizing with Design Compiler
    • hw1.dcsh - Command script for Design Compiler, used by hw1_syn.csh

    You will need to submit your own versions of these 5 files to get full credit for this assignment.
  3. Type the command "add cadence" to add the Verilog-XL simulator to your path.
  4. Source the script hw1_sim.csh. This script begins by invoking the dirSetup.py python script (which was added to your path by the course setup script) to create a run directory called run/vxl. Then it changes to this directory and runs a simulation to create the a value-change dump-file called hw1.vcd.
  5. Change to the run/vxl directory and view the waveform file with the command signalscan hw1.vcd &. For information on how to use this program, refer to pages 8-10 of the ECE520 Tutorial, or see the Signalscan Waves User Guide.
  6. Change back to your original run directory and examine the file hw1_syn.csh. Note that this script does the following things:
    • Runs the dirSetup.py script again to create a run-directory for Design Compiler called run/dc. It also creates a .synopsys_dc.setup file in this directory that is automatically configured to use the standard-cell library with worst-case timing values.
    • Invokes Design Compiler to execute the script hw1.dcsh and redirects the output to the file hw1.log. Note also that this command is timed. Keeping track of tool execution times is very important for creating and optimizing automated design flows.
    • Invokes the sysinfo.csh script, which is another script made specially for this class. This script simply dumps information about the machine you're working on in order to make sense of the recorded execution time. This information includes the number of processors and their speed and the amount of virtual and core memory.
    • Dumps the disk usage of the current directory and your Synopsys cache directory into the files run.du and cache.du. Keeping track of disk space is also very important for creating an automated flow.
  7. Examine the file hw1.dcsh. This script does the following:
    • Reads the verilog netlist. You will need to change the source file to your own.
    • Sets the clock period to 900 ps. You will need to set this to target clock period for your design.
    • Compiles the design, mapping it to our standard-cell library.
    • Reports the area in the area.rpt file. You can find the number of cells in this file. Remember that it should be between 200 and 1000 for this assignment.
    • Reports the critical-path delay in the file timing_worst.rpt.
    • Saves the file in both Verilog and Synopsys formats. You will need to change the names of the target files when creating your own design.
    • Translates (re-links) the design with the best-case (fast process) timing library.
    • Reports the best-case critical-path delay in the file timing_best.rpt.
    You can get information about any of the commands in this script by typing "help [command]" in dc_shell.
  8. Type the command "add synopsys" to add Design Compiler to your path.
  9. Source the script hw1_syn.csh. This will synthesize the design and create all of the files mentioned above.
  10. Here is the output that I get when I run this tutorial. Your output will differ slightly, since you'll be using a different machine and probably have different stuff in your Synopsys Cache.

Additional Documentation

You can find documentation for the tools used in this tutorial with the following commands:

  • The ECE520 Tutorial 1: Introduction to ASIC Deisign Methodology is a great 32-page introduction and reference.
  • The Cadence documentation browser can be started with the command cdsdoc & . From here, you can reach the following documents:
    • Verilog-XL User Guide - Set the active document hierarchy to "LDV 3.1" and select Verilog-XL -> Verilog-XL User Guide
    • Verilog-XL Reference - Set the active document hierarchy to "LDV 3.1" and select Verilog-XL -> Verilog-XL Reference
    • Signalscan Waves User Guide - Set the active document hierarchy to "LDV 3.1" and select Signalscan TX -> Signalscan Waves User Guide
  • The Synopsys online documentation can be started with the command sold & - From here, you can reach the following documents:
    • Design Compiler User Guide - Synthesis Tools: Core Synthesis -> Design Compiler : Design Compiler User Guide
    • Design Compiler Reference Manual: Optimization and Timing Analysis - Synthesis Tools: Core Synthesis -> Design Compiler : Design Compiler Reference Manual: Optimization and Timing Analysis

Submission

You should turn in a .tar.gz archive containing the following files:

  1. The RTL code you used to synthesize your design (Verilog, VHDL or Module Compiler code, analagous to the addreg_behav.v file above)
  2. The test-bench used to simulate your design (Verilog or VHDL code, analagous to the tb.v file above). If you used Module Compiler code for (1), then you must include the behavioral model here as well.
  3. Your own hw1_sim.csh file. It need not match the one provided with the tutorial above, but it must run a simulation flawlessly using the simulator of your choice.
  4. Although not required, you may include a waveform file (such as the hw1.vcd file above) for extra credit.
  5. Your own hw1_syn.csh file, which must flawlessly synthesize the design. This file need not match the one provided in the tutorial, but it must generate the hw1.log, run.du, and cache.du files.
  6. Your own hw1.log file, which must include the dc_shell execution time and the output of the sysinfo.csh script.
  7. Your own run.du file
  8. Your own cache.du file
  9. Your own hw1.dcsh file, which must flawlessly synthesize the design. This file need not match the one provided in the tutorial, but it must generate the area.rpt, timing_worst.rpt, and timing_best.rpt files, along with a Verilog netlist.
  10. The Verilog Netlist for your synthesized design
  11. Your own area.rpt file
  12. Your own timing_worst.rpt file
  13. Your own timing_best.rpt file
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