read -format verilog ../../addreg_behav.v
create_clock -period 900 CLK
compile
report_area > area.rpt
report_timing > timing_worst.rpt
write -output addreg_netl.db
write -format verilog -output addreg_netl.v
target_library = { ncsulib25_best.db }
translate
report_timing > timing_best.rpt
exit