`resetall
`celldefine
`delay_mode_path
`timescale 100ps/100ps

module tb;
  reg CLK;
  reg [3:0] A,B;
  wire [3:0] Z;

  addreg dut(A,B,CLK,Z);

  initial
  begin
    $dumpfile("hw1.vcd");
    $dumpvars(1,CLK,A,B,Z);
    CLK = 1;
    #10 A = 4'd0; B = 4'd0;
    #10 A = 4'd1; B = 4'd0;
    #10 A = 4'd0; B = 4'd2;
    #10 A = 4'd3; B = 4'd0;
    #10 A = 4'd0; B = 4'd4;
    #10 A = 4'd5; B = 4'd0;
    #10 A = 4'd0; B = 4'd6;
    #10 A = 4'd7; B = 4'd0;
    #10 A = 4'd1; B = 4'd1;
    #10 $finish;
  end

  always #5 CLK = ~CLK;

endmodule

`endcelldefine