Information: Updating design information... (UID-85)
 
****************************************
Report : timing
        -path full
        -delay max
        -max_paths 1
Design : addreg
Version: 2001.08
Date   : Sun Jan 12 08:12:08 2003
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Operating Conditions: 
Wire Load Model Mode: top

  Startpoint: A[2] (input port)
  Endpoint: Z_reg[3] (rising edge-triggered flip-flop clocked by CLK)
  Path Group: CLK
  Path Type: max

  Point                                    Incr       Path
  -----------------------------------------------------------
  clock (input port clock) (rise edge)     0.00       0.00
  input external delay                     0.00       0.00 f
  A[2] (in)                                0.00       0.00 f
  U15/op (inv_4)                          15.06      15.06 r
  U8/op (nand2_2)                         28.14      43.20 f
  U7/op (and2_2)                          34.71      77.91 f
  U18/op (nor3_2)                         70.96     148.87 r
  U19/op (xor2_2)                         39.72     188.58 f
  Z_reg[3]/ip (dp_2)                       0.00     188.58 f
  data arrival time                                 188.58

  clock CLK (rise edge)                  900.00     900.00
  clock network delay (ideal)              0.00     900.00
  Z_reg[3]/ck (dp_2)                       0.00     900.00 r
  library setup time                     -97.77     802.23
  data required time                                802.23
  -----------------------------------------------------------
  data required time                                802.23
  data arrival time                                -188.58
  -----------------------------------------------------------
  slack (MET)                                       613.64