****************************************
Report : timing
        -path full
        -delay max
        -max_paths 1
Design : addreg
Version: 2001.08
Date   : Sun Jan 12 08:12:06 2003
****************************************

Operating Conditions: 
Wire Load Model Mode: top

  Startpoint: A[1] (input port)
  Endpoint: Z_reg[3] (rising edge-triggered flip-flop clocked by CLK)
  Path Group: CLK
  Path Type: max

  Point                                    Incr       Path
  -----------------------------------------------------------
  clock (input port clock) (rise edge)     0.00       0.00
  input external delay                     0.00       0.00 f
  A[1] (in)                                0.00       0.00 f
  U6/op (and2_2)                         111.57     111.57 f
  U7/op (and2_2)                         128.90     240.47 f
  U18/op (nor3_2)                        232.50     472.96 r
  U19/op (xor2_2)                        165.14     638.10 f
  Z_reg[3]/ip (dp_2)                       0.00     638.10 f
  data arrival time                                 638.10

  clock CLK (rise edge)                  900.00     900.00
  clock network delay (ideal)              0.00     900.00
  Z_reg[3]/ck (dp_2)                       0.00     900.00 r
  library setup time                    -243.73     656.27
  data required time                                656.27
  -----------------------------------------------------------
  data required time                                656.27
  data arrival time                                -638.10
  -----------------------------------------------------------
  slack (MET)                                        18.17