ECE 741: Sequential Machines
Homework #2 - Spring 2003Assignment
- Choose two papers from the IEEE Journal of Solid State Circuits (JSSC) and/or the International Solid State Circuits Conference (ISSCC) that implement a similar function on a chip. Compare the performance of the architectures in terms of area efficiency (OPS/mm2) and energy efficiency (OPS/mW) when scaled to 0.13 um as demonstrated in class. The the circuits must be implemented in different process generations and neither may be older than 1.0 um. Be sure to comment on any factors that may affect your analysis and make an attempt to explain why one architecture may be better than another.
Tips:
- To search through the tables of contents of the these journals and conference proceedings, go to IEEE Xplore, choose Search -> Advanced, and enter the following string:
(solid state circuits <in> jn) <and> (table of contents <in> ti)
Note that you may have to do this from a workstation on the NCSU campus in order to have access to the on-line PDF files that IEEE Xplore serves.
- Your results should be reported in the form of an HTML table similar to the one in the example given below (cut and paste this one from this page's HTML source code):
| Function: |
MPEG-4 Encoding |
| 1st paper: |
M. Takahashi et al, "A 60 mW MPEG4 video codec using clustered voltage scaling with variable supply-voltage scheme," ISSCC Digest of Technical Papers, 1998, pp. 36-37. |
| 2nd paper: |
T. Hashimoto et al, "A 90mW MPEG4 Video Codec LSI with the Capability for Core Profile," ISSCC Digest of Technical Papers, 2001, pp. 140-141. |
Throughput
(QCIF frames / sec.) |
Area |
Power |
Efficiency |
| paper |
Lg |
VDD |
original |
scaled
to 0.13 um |
original |
scaled
to 0.13 um |
original |
scaled
to 0.13 um |
area efficiency |
energy efficiency |
| 1 |
0.3 um |
2.5 V |
10 |
27.7 |
81 mm2 |
15.2 mm2 |
60 mW |
25.0 mW |
1.82 OPS/mm2 |
1.11 OPS/mW |
| 2 |
0.18 um |
1.8 V |
15 |
20.8 |
75.7 mm2 |
39.5 mm2 |
90 mW |
60.1 mW |
0.527 OPS/mm2 |
0.346 OPS/mW |
| Comments: |
- The circuit in paper 1 actually uses two supply voltages, 2.5 V and 1.75 V. The numbers shown assume 2.5 V was used throughout. If 1.75 V were assumed, the scaled throughput and power would be 39.6 frames/sec and 72.8 mW, which would give an area efficiency of 2.60 OPS/mm2 and an energy efficiency of 0.544 OPS/mW.
- The circuit in paper 2 implements the "core profile" function in addition to MPEG-4 encoding, which could account for its reduced area and energy efficiency.
- The circuit in paper 2 also includes 20 MB of embedded DRAM, which reduces its area efficiency considerably. Paper 1 uses an external memory, which is not included in these calculations. This omission makes the circuit in paper 1 seem artificially better.
|
- Consider an NxN array of 4-terminal cells connected to their nearest diagonal neighbors. The figure below illustrates this case for N=3.
- Use Rent's rule to find an expression for the parallelism constant p of this array in terms of N.
- Calculate p for N=2
- Find the limit of p as N -> infinity.
- Using Donath's method, find the average interconnect length Lavg for N=10 and N=1000 (assume davg = 1)
- Is it appropriate to use Donath's method to estimate the Lavg for this structure? Why or why not?
Report your results in the following HTML table:
| expression for p |
(your answer here) |
| for N=2, p= |
(your answer here) |
| for N->inf, p= |
(your answer here) |
| for N=10, Lavg= |
(your answer here) |
| for N=1000, Lavg= |
(your answer here) |
| Comments: |
(your answer to the final question here) |
Submission
You should turn in a single
.html file containing the two tables described above. Only the tables are required. You are not required to include complete HTML tags (such as <head> and <body>).
3DIC Project