ECE 741: Sequential Machines

Homework #3 - Spring 2003Assignment

1. Answer the following questions, based on the Sylvester & Keutzer 2000 paper:
   • What is the pitch of the "fat" wires at each technology node in Fig. 6? (Your answer should be a list of numbers)
   • What are Smin and W are in Table II? (Your answer should be an explanation, rather than actual numbers)
2. Compare the critical-path delay of your design from HW#1 with and without wire-load models. Then place & route your design using First Encounter and generate capacitance and resistance back-annotation files for Design Compiler. Write a simple Python script to fix an error in one of these files. Finally, back-annotate these parasitics in Design Compiler and compare the post-route critical-path delay.

Tutorial

The following is a brief tutorial with example files to illustrate what is expected for problem 2.

1. Source the MUSE setup script as described in HW#1
2. Create a run directory for this assignment and copy the following files into this directory:
   • counter_netl.v - Verilog netlist for a 4-bit counter
   • hw3_prerte.csh - Script for generating timing reports with Design Compiler
   • hw3_prerte.dcsh - Command script for Design Compiler, used by the shell script
   • counter.tc - Timing constraints for this design used by First Encounter (basically the same as in hw3_prerte.dcsh)
   • hw3_postrte.csh - Script for generating post-route timing reports
   • hw3_postrte.dcsh - Post-route command script for Design Compiler
   • regexp.py - Python example script demonstrating regular expressions
   • example.txt - Example input for the Python script
3. Examine the file hw3_prerte.dcsh. Note that this file reads in the verilog netlist, sets the timing constraint, and reports the worst-case critical path delay. Then it switches to the library with wire-load models and re-generates the timing report.
4. Type the command "add synopsys" to add Design Compiler to your path.
5. Source the script hw3_prerte.csh. This will generate timing reports as mentioned above.
6. Compare the files timing_prerte.rpt and timing_prerte_wl.rpt in the run/dc directory. Note that the timing slack was 408.64ps before wire-load models were used, and -118.89ps after they were added. Wires have slowed things down! Note also that the critical path is identical for these two cases. The first output is value_reg[0]/q, and the last input is value_reg[2]/ip. There are 13 segments in-between these endpoints, which are the same in both cases. This may not be the case for your design, as wire-load models tend to make paths with more segments seem worse than those with fewer segments.
7. Change to the directory run/fe.
8. Add First Encounter to your path by typing add cadence
9. Start First Encounter with the command encounter.
10. Choose Design -> Design Import and click "Load" at the bottom of the next pop-up window. Browse and choose the file "vlogin.conf". This file was created by the setup script to set many of the default options for this operation. You'll need to make the following changes:
    • Set Netlist -> Verilog Files to ../../counter_netl.v
    • Select Netlist -> Top Cell: By User and set the value to counter
    • Set Timing Information -> Timing Constraint File to ../../counter.tc
11. Click "OK" to close the dialog box and import the design.
12. At this point, your design should look like the figure below. You can zoom in by right-clicking and draging a box, and pan by middle-clicking and dragging. Some convenient key-bindings are included below.
    
    

    Key	Action	Description
    q	Attribute	Display the object attribute form on selected object.
    f	Fit Display	Zooms the display to fit the design area.
    g	Group	Moves up the hierarchy on the highlighted Hinstance.
    u	Ungroup	Moves down the hierarchy on the highlighted Hinstance.
    v	View DB	View the attributes of highlighted object.
    z	Zoom-in	Zooms in the display, 2x.
    Z	Zoom-out	Zooms out the display, 2x.
    Shift	Select	Allows multiple selections of objects.
    Arrows	Pan	Pans the display in direction of arrow.
    Delete	Ruler	Removes last ruler displayed.
    Space Bar	Focus	Changes the focus of overlapping objects

13. Choose Place -> Place... to run the Amoeba Placer. Click OK on the next pop-up to run placement with default options. Once complete, Toggle between the views with View -> View -> Floorplan View and View -> View -> Placement View. They should look similar to the pictures below. Note that in the "Floorplan View", the triangles on the edges indicate the location of boundary pins, the interface for this block.
    
14. Choose Design -> Save Design and save as "counter_placed.enc".
15. In the terminal window where you typed the encounter command, you should see a command prompt (assuming you didn't run this process in the background!). Type the following command at this prompt:
    addFiller -cell filler -prefix fill -fillBoundary
    Filler-cells should be added to the design. These cells ensure that power is connected in the standard-cell rows and that no design-rule errors occur in the gaps between placed cells. The design should look similar to the picture below.
    
16. Choose Route -> Trial Route and click OK on the next pop-up to route with default options. Your routed design should look like the one below:
    
17. Choose Design -> Save Design and save as "counter_routed.enc".
18. Choose Timing -> Extract RC. On the next pop-up, select the "Save Setload" and "Save Set Resistance" buttons. This will generate the counter.setload and counter.setres back-annotation scripts for dc_shell. Click OK.
19. Choose Design -> Exit to quit First Encounter.
20. Copy the files counter.setload and counter.setres into the run/dc directory.
21. Change back to the top directory and examine the file hw3_postrte.dcsh. This file is much like the pre-route version except that it loads the counter.setload file and generates a timing report with these back-annotated capacitance values. Then it loads the counter.setres file to back-annotate resistances and generates another report for comparison.
22. Source the script hw3_postrte.csh.
23. Examine the file timing_postrte_caponly.rpt file in the run/dc directory. Note that the slack is now 408.42ps. This is less than 1ps different from the original slack without wire-loads! Something is wrong.
24. Examine the file $MUSE_HOME/tech/TSMC025_deep/ncsulib25_worst.lib. Scan down to the line that reads "capacitive_load_unit" and note that the unit of capacitance is femto-farads. Now examine the file counter.setload and note that the unit is pico-farads. In order to back-annotate correctly, we need to multiply the capacitance values in the back-annotation file by a factor of 1000.
25. Examine the file regexp.py. This script parses the input line-by-line looking for lines that contain only digits. Then it multiplies that number by 1000 and prints it out. If the pattern is not recognized, then it prints out the line with no modification.
26. Execute the command python regexp.py < example.txt > out.txt and examine the file out.txt. Note that the number with the decimal point was not matched by this regular expression. You will need to modify this regular expression and the print statement in order to fix the counter.setload file.
27. Modify the regexp.py into the file fixcap.py. You will need to turn in this script and re-use it on your own design.
28. Change to the run/dc directory and execute the command python fixcap.py < ../fe/counter.setload > counter.setload.
29. Change back to the top directory and source the hw3_postrte.csh script again.
30. Now examine the files timing_postrte_caponly.rpt and timing_postrte_rc.rpt. Note that the slack in these files is 179.82ps and 177.16ps respectively, which makes more sense than the earlier value. Since the wires in this block are very short, the resistance has little effect. You may observe something different for your design, however.
31. Here is the output that I get when I run this tutorial.
    • hw3.log
    • timing_prerte.rpt
    • timing_prerte_wl.rpt
    • counter.setload (original)
    • counter.setload (fixed)
    • counter.setres
    • timing_postrte_caponly.rpt
    • timing_postrte_rc.rpt

Additional Documentation

• Additional First Encounter documentation can be found by choosing "Help" from the menu. This starts a web-browser to view the HTML documentation.
• Additional Python documentation can be found in the lecture reading assignments.

Submission

You should turn in a .tar.gz archive containing the following files:

1. The Verilog Netlist used
2. Your own hw3_prerte.csh, hw3_prerte.dcsh, hw3_postrte.csh, and hw3_postrte.dcsh files. They need not match the ones provided with the tutorial above, but they must run flawlessly to generate your report and log files.
3. Your own hw3.log file.
4. Your own timing_prerte.rpt, timing_prerte_wl.rpt, timing_postrte_caponly.rpt, and timing_postrte_rc.rpt files.
5. Your own fixcap.py script
6. Your own fixed .setload and .setres files.
7. A file called hw3.html that contains a table with your answers to the reading questions and a summary of the different slack values. Your table should be similar to the one given below:
   
   

   Answer to question #1
   Answer to question #2
   Timing Check	First output instance/pin	Segments in timing path	Last input instance/pin	Slack
   prerte	value_reg[0]/q	13	value_reg[2]/ip	408.64ps
   prerte_wl	value_reg[0]/q	13	value_reg[2]/ip	-118.89ps
   postrte_caponly	value_reg[0]/q	13	value_reg[2]/ip	179.82ps
   postrte_rc	value_reg[0]/q	13	value_reg[2]/ip	177.16ps