Behavioral Compiler (TM)
                        DC Professional (TM)
                           DC Expert (TM)
                            DC Ultra (TM)
                         VHDL Compiler (TM)
                          HDL Compiler (TM)
                        Library Compiler (TM)
                         Power Compiler (TM)
                          DFT Compiler (TM)
                         Test Compiler (TM)
                            BSD Compiler
                      DesignWare Developer (TM)
                          DesignPower (TM)

            Version 2001.08 for sparcOS5 -- Aug 08, 2001
              Copyright (c) 1988-2001 by Synopsys, Inc.
                         ALL RIGHTS RESERVED

This program is proprietary and confidential information of Synopsys, Inc.
and may be used and disclosed only as authorized in a license agreement
controlling such use and disclosure.

Initializing...
read -format verilog ../../counter_netl.v
Loading verilog file '/afs/eos.ncsu.edu/lockers/research/ece/wdavis/users/wdavis/build/ece741/examples/hw3/counter_netl.v'
Running PRESTO HDLC
Loading db file '/afs/bp.ncsu.edu/dist/synopsys200108/libraries/syn/standard.sldb'
Loading db file '/afs/bp.ncsu.edu/dist/synopsys200108/libraries/syn/gtech.db'
Loading db file '/afs/eos.ncsu.edu/lockers/workspace/ece/ece741/001/common/TSMC025_deep/ncsulib25_worst.db'
Compiling source netlist file /afs/eos.ncsu.edu/lockers/research/ece/wdavis/users/wdavis/build/ece741/examples/hw3/counter_netl.v
Presto compilation completed successfully.
Current design is now '/afs/eos.ncsu.edu/lockers/research/ece/wdavis/users/wdavis/build/ece741/examples/hw3/counter.db:counter'
{"counter"}
create_clock -period 3000 clock
Performing create_clock on port 'clock'. 
1
report_timing > timing_prerte.rpt
1
target_library = { ncsulib25_worst_wl.db }
{"ncsulib25_worst_wl.db"}
translate
Loading db file '/afs/eos.ncsu.edu/lockers/workspace/ece/ece741/001/common/TSMC025_deep/ncsulib25_worst_wl.db'

  Loading target library 'ncsulib25_worst'
  Loading design 'counter'
Information: Changed wire load model for 'counter' from 'noload' to 'areaunder5K'. (OPT-170)
  Translating Design 'counter'
    from the technology 'ncsulib25' (cmos) 
    to the technology 'ncsulib25_worst' (cmos) 

  Transferring Design 'counter' to database 'counter.db'
Current design is 'counter'.
1
report_timing > timing_prerte_wl.rpt
1
exit
1
dc_shell> 
Thank you...

real       32.0
user        4.1
sys         2.6

                      Behavioral Compiler (TM)
                        DC Professional (TM)
                           DC Expert (TM)
                            DC Ultra (TM)
                         VHDL Compiler (TM)
                          HDL Compiler (TM)
                        Library Compiler (TM)
                         Power Compiler (TM)
                          DFT Compiler (TM)
                         Test Compiler (TM)
                            BSD Compiler
                      DesignWare Developer (TM)
                          DesignPower (TM)

            Version 2001.08 for sparcOS5 -- Aug 08, 2001
              Copyright (c) 1988-2001 by Synopsys, Inc.
                         ALL RIGHTS RESERVED

This program is proprietary and confidential information of Synopsys, Inc.
and may be used and disclosed only as authorized in a license agreement
controlling such use and disclosure.

Initializing...
read -format verilog ../../counter_netl.v
Loading verilog file '/afs/eos.ncsu.edu/lockers/research/ece/wdavis/users/wdavis/build/ece741/examples/hw3/counter_netl.v'
Running PRESTO HDLC
Loading db file '/afs/bp.ncsu.edu/dist/synopsys200108/libraries/syn/standard.sldb'
Loading db file '/afs/bp.ncsu.edu/dist/synopsys200108/libraries/syn/gtech.db'
Loading db file '/afs/eos.ncsu.edu/lockers/workspace/ece/ece741/001/common/TSMC025_deep/ncsulib25_worst.db'
Compiling source netlist file /afs/eos.ncsu.edu/lockers/research/ece/wdavis/users/wdavis/build/ece741/examples/hw3/counter_netl.v
Presto compilation completed successfully.
Current design is now '/afs/eos.ncsu.edu/lockers/research/ece/wdavis/users/wdavis/build/ece741/examples/hw3/counter.db:counter'
{"counter"}
create_clock -period 3000 clock
Performing create_clock on port 'clock'. 
1
include counter.setload
/*
  set_load for design counter
  Format: for capacitance: set_load <cap in pf> <netName>
  Capacitance Scale Factor: 1.000000
*/
auto_link_disable = true
"true"
set_load 0.002 "in[3]"
Performing set_load on port 'in[3]'. 
1
set_load 0.001 "in[2]"
Performing set_load on port 'in[2]'. 
1
set_load 0.001 "in[1]"
Performing set_load on port 'in[1]'. 
1
set_load 0.002 "in[0]"
Performing set_load on port 'in[0]'. 
1
set_load 0.009 "clock"
Performing set_load on port 'clock'. 
1
set_load 0.008 "latch"
Performing set_load on port 'latch'. 
1
set_load 0.001 "dec"
Performing set_load on port 'dec'. 
1
set_load 0.003 "zero"
Performing set_load on port 'zero'. 
1
set_load 0.006 "value[3]"
Performing set_load on net 'value[3]'. 
1
set_load 0.007 "value[2]"
Performing set_load on net 'value[2]'. 
1
set_load 0.010 "value[1]"
Performing set_load on net 'value[1]'. 
1
set_load 0.004 "value[0]"
Performing set_load on net 'value[0]'. 
1
set_load 0.005 "n3"
Performing set_load on net 'n3'. 
1
set_load 0.003 "n5"
Performing set_load on net 'n5'. 
1
set_load 0.005 "n6"
Performing set_load on net 'n6'. 
1
set_load 0.002 "n7"
Performing set_load on net 'n7'. 
1
set_load 0.006 "n8"
Performing set_load on net 'n8'. 
1
set_load 0.001 "n9"
Performing set_load on net 'n9'. 
1
set_load 0.002 "n10"
Performing set_load on net 'n10'. 
1
set_load 0.006 "n11"
Performing set_load on net 'n11'. 
1
set_load 0.002 "n12"
Performing set_load on net 'n12'. 
1
set_load 0.001 "n13"
Performing set_load on net 'n13'. 
1
set_load 0.008 "n14"
Performing set_load on net 'n14'. 
1
set_load 0.005 "n15"
Performing set_load on net 'n15'. 
1
set_load 0.006 "n16"
Performing set_load on net 'n16'. 
1
set_load 0.008 "n17"
Performing set_load on net 'n17'. 
1
set_load 0.002 "n18"
Performing set_load on net 'n18'. 
1
set_load 0.001 "n19"
Performing set_load on net 'n19'. 
1
set_load 0.001 "n20"
Performing set_load on net 'n20'. 
1
set_load 0.005 "n21"
Performing set_load on net 'n21'. 
1
set_load 0.003 "n22"
Performing set_load on net 'n22'. 
1
set_load 0.001 "n23"
Performing set_load on net 'n23'. 
1
set_load 0.007 "n24"
Performing set_load on net 'n24'. 
1
set_load 0.005 "n25"
Performing set_load on net 'n25'. 
1
set_load 0.004 "n26"
Performing set_load on net 'n26'. 
1
set_load 0.003 "n27"
Performing set_load on net 'n27'. 
1
set_load 0.004 "n28"
Performing set_load on net 'n28'. 
1
set_load 0.005 "n29"
Performing set_load on net 'n29'. 
1
set_load 0.004 "n30"
Performing set_load on net 'n30'. 
1
set_load 0.004 "n31"
Performing set_load on net 'n31'. 
1
set_load 0.006 "n32"
Performing set_load on net 'n32'. 
1
set_load 0.002 "n33"
Performing set_load on net 'n33'. 
1
set_load 0.009 "n34"
Performing set_load on net 'n34'. 
1
set_load 0.003 "n35"
Performing set_load on net 'n35'. 
1
set_load 0.001 "n36"
Performing set_load on net 'n36'. 
1
set_load 0.003 "n37"
Performing set_load on net 'n37'. 
1
set_load 0.000 "n38"
Performing set_load on net 'n38'. 
1
set_load 0.005 "n39"
Performing set_load on net 'n39'. 
1
set_load 0.001 "n40"
Performing set_load on net 'n40'. 
1
set_load 0.008 "n41"
Performing set_load on net 'n41'. 
1
set_load 0.002 "n42"
Performing set_load on net 'n42'. 
1


auto_link_disable = false
"false"
1
report_timing > timing_postrte_caponly.rpt
1
include counter.setres
/*
  set_resistance for design counter
  Format: for resistance: set_resistance <res in Kohm> <netName>
  Resistance Scale Factor: 1.000000
*/
auto_link_disable = true
"true"
set_resistance 0.011 "in[3]"
Performing set_resistance on net 'in[3]'. 
1
set_resistance 0.010 "in[2]"
Performing set_resistance on net 'in[2]'. 
1
set_resistance 0.005 "in[1]"
Performing set_resistance on net 'in[1]'. 
1
set_resistance 0.011 "in[0]"
Performing set_resistance on net 'in[0]'. 
1
set_resistance 0.041 "clock"
Performing set_resistance on net 'clock'. 
1
set_resistance 0.060 "latch"
Performing set_resistance on net 'latch'. 
1
set_resistance 0.005 "dec"
Performing set_resistance on net 'dec'. 
1
set_resistance 0.028 "zero"
Performing set_resistance on net 'zero'. 
1
set_resistance 0.030 "value[3]"
Performing set_resistance on net 'value[3]'. 
1
set_resistance 0.034 "value[2]"
Performing set_resistance on net 'value[2]'. 
1
set_resistance 0.039 "value[1]"
Performing set_resistance on net 'value[1]'. 
1
set_resistance 0.021 "value[0]"
Performing set_resistance on net 'value[0]'. 
1
set_resistance 0.032 "n3"
Performing set_resistance on net 'n3'. 
1
set_resistance 0.021 "n5"
Performing set_resistance on net 'n5'. 
1
set_resistance 0.024 "n6"
Performing set_resistance on net 'n6'. 
1
set_resistance 0.011 "n7"
Performing set_resistance on net 'n7'. 
1
set_resistance 0.026 "n8"
Performing set_resistance on net 'n8'. 
1
set_resistance 0.017 "n9"
Performing set_resistance on net 'n9'. 
1
set_resistance 0.019 "n10"
Performing set_resistance on net 'n10'. 
1
set_resistance 0.026 "n11"
Performing set_resistance on net 'n11'. 
1
set_resistance 0.011 "n12"
Performing set_resistance on net 'n12'. 
1
set_resistance 0.018 "n13"
Performing set_resistance on net 'n13'. 
1
set_resistance 0.020 "n14"
Performing set_resistance on net 'n14'. 
1
set_resistance 0.024 "n15"
Performing set_resistance on net 'n15'. 
1
set_resistance 0.025 "n16"
Performing set_resistance on net 'n16'. 
1
set_resistance 0.040 "n17"
Performing set_resistance on net 'n17'. 
1
set_resistance 0.019 "n18"
Performing set_resistance on net 'n18'. 
1
set_resistance 0.018 "n19"
Performing set_resistance on net 'n19'. 
1
set_resistance 0.018 "n20"
Performing set_resistance on net 'n20'. 
1
set_resistance 0.039 "n21"
Performing set_resistance on net 'n21'. 
1
set_resistance 0.012 "n22"
Performing set_resistance on net 'n22'. 
1
set_resistance 0.017 "n23"
Performing set_resistance on net 'n23'. 
1
set_resistance 0.043 "n24"
Performing set_resistance on net 'n24'. 
1
set_resistance 0.036 "n25"
Performing set_resistance on net 'n25'. 
1
set_resistance 0.022 "n26"
Performing set_resistance on net 'n26'. 
1
set_resistance 0.020 "n27"
Performing set_resistance on net 'n27'. 
1
set_resistance 0.022 "n28"
Performing set_resistance on net 'n28'. 
1
set_resistance 0.024 "n29"
Performing set_resistance on net 'n29'. 
1
set_resistance 0.014 "n30"
Performing set_resistance on net 'n30'. 
1
set_resistance 0.023 "n31"
Performing set_resistance on net 'n31'. 
1
set_resistance 0.025 "n32"
Performing set_resistance on net 'n32'. 
1
set_resistance 0.011 "n33"
Performing set_resistance on net 'n33'. 
1
set_resistance 0.057 "n34"
Performing set_resistance on net 'n34'. 
1
set_resistance 0.020 "n35"
Performing set_resistance on net 'n35'. 
1
set_resistance 0.018 "n36"
Performing set_resistance on net 'n36'. 
1
set_resistance 0.020 "n37"
Performing set_resistance on net 'n37'. 
1
set_resistance 0.000 "n38"
Performing set_resistance on net 'n38'. 
1
set_resistance 0.023 "n39"
Performing set_resistance on net 'n39'. 
1
set_resistance 0.017 "n40"
Performing set_resistance on net 'n40'. 
1
set_resistance 0.040 "n41"
Performing set_resistance on net 'n41'. 
1
set_resistance 0.019 "n42"
Performing set_resistance on net 'n42'. 
1


auto_link_disable = false
"false"
1
report_timing > timing_postrte_rc.rpt
1
exit
1
dc_shell> 
Thank you...

real       28.3
user        2.6
sys         2.8

                      Behavioral Compiler (TM)
                        DC Professional (TM)
                           DC Expert (TM)
                            DC Ultra (TM)
                         VHDL Compiler (TM)
                          HDL Compiler (TM)
                        Library Compiler (TM)
                         Power Compiler (TM)
                          DFT Compiler (TM)
                         Test Compiler (TM)
                            BSD Compiler
                      DesignWare Developer (TM)
                          DesignPower (TM)

            Version 2001.08 for sparcOS5 -- Aug 08, 2001
              Copyright (c) 1988-2001 by Synopsys, Inc.
                         ALL RIGHTS RESERVED

This program is proprietary and confidential information of Synopsys, Inc.
and may be used and disclosed only as authorized in a license agreement
controlling such use and disclosure.

Initializing...
read -format verilog ../../counter_netl.v
Loading verilog file '/afs/eos.ncsu.edu/lockers/research/ece/wdavis/users/wdavis/build/ece741/examples/hw3/counter_netl.v'
Running PRESTO HDLC
Loading db file '/afs/bp.ncsu.edu/dist/synopsys200108/libraries/syn/standard.sldb'
Loading db file '/afs/bp.ncsu.edu/dist/synopsys200108/libraries/syn/gtech.db'
Loading db file '/afs/eos.ncsu.edu/lockers/workspace/ece/ece741/001/common/TSMC025_deep/ncsulib25_worst.db'
Compiling source netlist file /afs/eos.ncsu.edu/lockers/research/ece/wdavis/users/wdavis/build/ece741/examples/hw3/counter_netl.v
Presto compilation completed successfully.
Current design is now '/afs/eos.ncsu.edu/lockers/research/ece/wdavis/users/wdavis/build/ece741/examples/hw3/counter.db:counter'
{"counter"}
create_clock -period 3000 clock
Performing create_clock on port 'clock'. 
1
include counter.setload
/*
  set_load for design counter
  Format: for capacitance: set_load <cap in pf> <netName>
  Capacitance Scale Factor: 1.000000
*/
auto_link_disable = true
"true"
set_load  2.0  "in[3]"
Performing set_load on port 'in[3]'. 
1
set_load  1.0  "in[2]"
Performing set_load on port 'in[2]'. 
1
set_load  1.0  "in[1]"
Performing set_load on port 'in[1]'. 
1
set_load  2.0  "in[0]"
Performing set_load on port 'in[0]'. 
1
set_load  9.0  "clock"
Performing set_load on port 'clock'. 
1
set_load  8.0  "latch"
Performing set_load on port 'latch'. 
1
set_load  1.0  "dec"
Performing set_load on port 'dec'. 
1
set_load  3.0  "zero"
Performing set_load on port 'zero'. 
1
set_load  6.0  "value[3]"
Performing set_load on net 'value[3]'. 
1
set_load  7.0  "value[2]"
Performing set_load on net 'value[2]'. 
1
set_load  10.0  "value[1]"
Performing set_load on net 'value[1]'. 
1
set_load  4.0  "value[0]"
Performing set_load on net 'value[0]'. 
1
set_load  5.0  "n3"
Performing set_load on net 'n3'. 
1
set_load  3.0  "n5"
Performing set_load on net 'n5'. 
1
set_load  5.0  "n6"
Performing set_load on net 'n6'. 
1
set_load  2.0  "n7"
Performing set_load on net 'n7'. 
1
set_load  6.0  "n8"
Performing set_load on net 'n8'. 
1
set_load  1.0  "n9"
Performing set_load on net 'n9'. 
1
set_load  2.0  "n10"
Performing set_load on net 'n10'. 
1
set_load  6.0  "n11"
Performing set_load on net 'n11'. 
1
set_load  2.0  "n12"
Performing set_load on net 'n12'. 
1
set_load  1.0  "n13"
Performing set_load on net 'n13'. 
1
set_load  8.0  "n14"
Performing set_load on net 'n14'. 
1
set_load  5.0  "n15"
Performing set_load on net 'n15'. 
1
set_load  6.0  "n16"
Performing set_load on net 'n16'. 
1
set_load  8.0  "n17"
Performing set_load on net 'n17'. 
1
set_load  2.0  "n18"
Performing set_load on net 'n18'. 
1
set_load  1.0  "n19"
Performing set_load on net 'n19'. 
1
set_load  1.0  "n20"
Performing set_load on net 'n20'. 
1
set_load  5.0  "n21"
Performing set_load on net 'n21'. 
1
set_load  3.0  "n22"
Performing set_load on net 'n22'. 
1
set_load  1.0  "n23"
Performing set_load on net 'n23'. 
1
set_load  7.0  "n24"
Performing set_load on net 'n24'. 
1
set_load  5.0  "n25"
Performing set_load on net 'n25'. 
1
set_load  4.0  "n26"
Performing set_load on net 'n26'. 
1
set_load  3.0  "n27"
Performing set_load on net 'n27'. 
1
set_load  4.0  "n28"
Performing set_load on net 'n28'. 
1
set_load  5.0  "n29"
Performing set_load on net 'n29'. 
1
set_load  4.0  "n30"
Performing set_load on net 'n30'. 
1
set_load  4.0  "n31"
Performing set_load on net 'n31'. 
1
set_load  6.0  "n32"
Performing set_load on net 'n32'. 
1
set_load  2.0  "n33"
Performing set_load on net 'n33'. 
1
set_load  9.0  "n34"
Performing set_load on net 'n34'. 
1
set_load  3.0  "n35"
Performing set_load on net 'n35'. 
1
set_load  1.0  "n36"
Performing set_load on net 'n36'. 
1
set_load  3.0  "n37"
Performing set_load on net 'n37'. 
1
set_load  0.0  "n38"
Performing set_load on net 'n38'. 
1
set_load  5.0  "n39"
Performing set_load on net 'n39'. 
1
set_load  1.0  "n40"
Performing set_load on net 'n40'. 
1
set_load  8.0  "n41"
Performing set_load on net 'n41'. 
1
set_load  2.0  "n42"
Performing set_load on net 'n42'. 
1


auto_link_disable = false
"false"
1
report_timing > timing_postrte_caponly.rpt
1
include counter.setres
/*
  set_resistance for design counter
  Format: for resistance: set_resistance <res in Kohm> <netName>
  Resistance Scale Factor: 1.000000
*/
auto_link_disable = true
"true"
set_resistance 0.011 "in[3]"
Performing set_resistance on net 'in[3]'. 
1
set_resistance 0.010 "in[2]"
Performing set_resistance on net 'in[2]'. 
1
set_resistance 0.005 "in[1]"
Performing set_resistance on net 'in[1]'. 
1
set_resistance 0.011 "in[0]"
Performing set_resistance on net 'in[0]'. 
1
set_resistance 0.041 "clock"
Performing set_resistance on net 'clock'. 
1
set_resistance 0.060 "latch"
Performing set_resistance on net 'latch'. 
1
set_resistance 0.005 "dec"
Performing set_resistance on net 'dec'. 
1
set_resistance 0.028 "zero"
Performing set_resistance on net 'zero'. 
1
set_resistance 0.030 "value[3]"
Performing set_resistance on net 'value[3]'. 
1
set_resistance 0.034 "value[2]"
Performing set_resistance on net 'value[2]'. 
1
set_resistance 0.039 "value[1]"
Performing set_resistance on net 'value[1]'. 
1
set_resistance 0.021 "value[0]"
Performing set_resistance on net 'value[0]'. 
1
set_resistance 0.032 "n3"
Performing set_resistance on net 'n3'. 
1
set_resistance 0.021 "n5"
Performing set_resistance on net 'n5'. 
1
set_resistance 0.024 "n6"
Performing set_resistance on net 'n6'. 
1
set_resistance 0.011 "n7"
Performing set_resistance on net 'n7'. 
1
set_resistance 0.026 "n8"
Performing set_resistance on net 'n8'. 
1
set_resistance 0.017 "n9"
Performing set_resistance on net 'n9'. 
1
set_resistance 0.019 "n10"
Performing set_resistance on net 'n10'. 
1
set_resistance 0.026 "n11"
Performing set_resistance on net 'n11'. 
1
set_resistance 0.011 "n12"
Performing set_resistance on net 'n12'. 
1
set_resistance 0.018 "n13"
Performing set_resistance on net 'n13'. 
1
set_resistance 0.020 "n14"
Performing set_resistance on net 'n14'. 
1
set_resistance 0.024 "n15"
Performing set_resistance on net 'n15'. 
1
set_resistance 0.025 "n16"
Performing set_resistance on net 'n16'. 
1
set_resistance 0.040 "n17"
Performing set_resistance on net 'n17'. 
1
set_resistance 0.019 "n18"
Performing set_resistance on net 'n18'. 
1
set_resistance 0.018 "n19"
Performing set_resistance on net 'n19'. 
1
set_resistance 0.018 "n20"
Performing set_resistance on net 'n20'. 
1
set_resistance 0.039 "n21"
Performing set_resistance on net 'n21'. 
1
set_resistance 0.012 "n22"
Performing set_resistance on net 'n22'. 
1
set_resistance 0.017 "n23"
Performing set_resistance on net 'n23'. 
1
set_resistance 0.043 "n24"
Performing set_resistance on net 'n24'. 
1
set_resistance 0.036 "n25"
Performing set_resistance on net 'n25'. 
1
set_resistance 0.022 "n26"
Performing set_resistance on net 'n26'. 
1
set_resistance 0.020 "n27"
Performing set_resistance on net 'n27'. 
1
set_resistance 0.022 "n28"
Performing set_resistance on net 'n28'. 
1
set_resistance 0.024 "n29"
Performing set_resistance on net 'n29'. 
1
set_resistance 0.014 "n30"
Performing set_resistance on net 'n30'. 
1
set_resistance 0.023 "n31"
Performing set_resistance on net 'n31'. 
1
set_resistance 0.025 "n32"
Performing set_resistance on net 'n32'. 
1
set_resistance 0.011 "n33"
Performing set_resistance on net 'n33'. 
1
set_resistance 0.057 "n34"
Performing set_resistance on net 'n34'. 
1
set_resistance 0.020 "n35"
Performing set_resistance on net 'n35'. 
1
set_resistance 0.018 "n36"
Performing set_resistance on net 'n36'. 
1
set_resistance 0.020 "n37"
Performing set_resistance on net 'n37'. 
1
set_resistance 0.000 "n38"
Performing set_resistance on net 'n38'. 
1
set_resistance 0.023 "n39"
Performing set_resistance on net 'n39'. 
1
set_resistance 0.017 "n40"
Performing set_resistance on net 'n40'. 
1
set_resistance 0.040 "n41"
Performing set_resistance on net 'n41'. 
1
set_resistance 0.019 "n42"
Performing set_resistance on net 'n42'. 
1


auto_link_disable = false
"false"
1
report_timing > timing_postrte_rc.rpt
1
exit
1
dc_shell> 
Thank you...

real        6.2
user        2.8
sys         1.0