Information: Updating design information... (UID-85) **************************************** Report : timing -path full -delay max -max_paths 1 Design : counter Version: 2001.08 Date : Thu Jan 30 19:21:40 2003 **************************************** * Some/all delay information is back-annotated. Operating Conditions: Wire Load Model Mode: top Startpoint: value_reg[0] (rising edge-triggered flip-flop clocked by clock) Endpoint: value_reg[2] (rising edge-triggered flip-flop clocked by clock) Path Group: clock Path Type: max Point Incr Path ----------------------------------------------------------- clock clock (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 value_reg[0]/ck (dp_2) 0.00 0.00 r value_reg[0]/q (dp_2) 343.51 343.51 f U47/op (buf_1) 274.74 618.25 f U9/op (nor2_2) 307.74 925.99 r U10/op (inv_4) 109.75 1035.74 f U11/op (nor3_2) 335.52 1371.26 r U12/op (inv_4) 66.09 1437.35 f U28/op (nand2_2) 83.58 1520.93 r U29/op (nand2_2) 203.01 1723.94 f U27/op (nand2_2) 148.73 1872.67 r U8/op (or2_2) 133.10 2005.77 r U33/op (mux2_2) 311.30 2317.07 r U43/op (buf_1) 154.25 2471.32 r U13/op (nand2_2) 108.18 2579.50 f value_reg[2]/ip (dp_2) 0.00 2579.50 f data arrival time 2579.50 clock clock (rise edge) 3000.00 3000.00 clock network delay (ideal) 0.00 3000.00 value_reg[2]/ck (dp_2) 0.00 3000.00 r library setup time -240.68 2759.32 data required time 2759.32 ----------------------------------------------------------- data required time 2759.32 data arrival time -2579.50 ----------------------------------------------------------- slack (MET) 179.82