Information: Updating design information... (UID-85) **************************************** Report : timing -path full -delay max -max_paths 1 Design : counter Version: 2001.08 Date : Thu Jan 30 18:09:57 2003 **************************************** Operating Conditions: Wire Load Model Mode: top Startpoint: value_reg[0] (rising edge-triggered flip-flop clocked by clock) Endpoint: value_reg[2] (rising edge-triggered flip-flop clocked by clock) Path Group: clock Path Type: max Point Incr Path ----------------------------------------------------------- clock clock (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 value_reg[0]/ck (dp_2) 0.00 0.00 r value_reg[0]/q (dp_2) 333.38 333.38 f U47/op (buf_1) 243.49 576.87 f U9/op (nor2_2) 263.21 840.09 r U10/op (inv_4) 98.42 938.51 f U11/op (nor3_2) 299.91 1238.41 r U12/op (inv_4) 54.02 1292.43 f U28/op (nand2_2) 72.12 1364.56 r U29/op (nand2_2) 182.62 1547.18 f U27/op (nand2_2) 135.38 1682.56 r U8/op (or2_2) 123.98 1806.54 r U33/op (mux2_2) 298.60 2105.14 r U43/op (buf_1) 153.18 2258.33 r U13/op (nand2_2) 95.22 2353.55 f value_reg[2]/ip (dp_2) 0.00 2353.55 f data arrival time 2353.55 clock clock (rise edge) 3000.00 3000.00 clock network delay (ideal) 0.00 3000.00 value_reg[2]/ck (dp_2) 0.00 3000.00 r library setup time -237.81 2762.19 data required time 2762.19 ----------------------------------------------------------- data required time 2762.19 data arrival time -2353.55 ----------------------------------------------------------- slack (MET) 408.64