Information: Updating design information... (UID-85)
 
****************************************
Report : timing
        -path full
        -delay max
        -max_paths 1
Design : counter
Version: 2001.08
Date   : Thu Jan 30 18:10:02 2003
****************************************

Operating Conditions: 
Wire Load Model Mode: enclosed

  Startpoint: value_reg[0]
              (rising edge-triggered flip-flop clocked by clock)
  Endpoint: value_reg[2]
            (rising edge-triggered flip-flop clocked by clock)
  Path Group: clock
  Path Type: max

  Des/Clust/Port     Wire Load Model       Library
  ------------------------------------------------
  counter            areaunder5K           ncsulib25_worst

  Point                                    Incr       Path
  -----------------------------------------------------------
  clock clock (rise edge)                  0.00       0.00
  clock network delay (ideal)              0.00       0.00
  value_reg[0]/ck (dp_2)                   0.00       0.00 r
  value_reg[0]/q (dp_2)                  347.63     347.63 f
  U47/op (buf_1)                         307.62     655.25 f
  U9/op (nor2_2)                         353.84    1009.09 r
  U10/op (inv_4)                         128.82    1137.92 f
  U11/op (nor3_2)                        392.87    1530.78 r
  U12/op (inv_4)                          69.14    1599.92 f
  U28/op (nand2_2)                        91.11    1691.04 r
  U29/op (nand2_2)                       244.14    1935.17 f
  U27/op (nand2_2)                       183.00    2118.17 r
  U8/op (or2_2)                          137.09    2255.26 r
  U33/op (mux2_2)                        320.93    2576.20 r
  U43/op (buf_1)                         177.52    2753.72 r
  U13/op (nand2_2)                       121.95    2875.67 f
  value_reg[2]/ip (dp_2)                   0.02    2875.70 f
  data arrival time                                2875.70

  clock clock (rise edge)               3000.00    3000.00
  clock network delay (ideal)              0.00    3000.00
  value_reg[2]/ck (dp_2)                   0.00    3000.00 r
  library setup time                    -243.19    2756.81
  data required time                               2756.81
  -----------------------------------------------------------
  data required time                               2756.81
  data arrival time                               -2875.70
  -----------------------------------------------------------
  slack (VIOLATED)                                 -118.89