Warning: Some timing arcs have been disabled for breaking timing loops or because of constant propagation. Use the 'report_disable_timing' command to get the list of these disabled timing arcs. (PTE-003) Warning: Failed to compute the RC network delay from the pin 'U15798/op' to the pin 'dbg_dat_o[15]' in the network 'dbg_dat_o[15]'. (RC-005) Warning: The type of RC delay calculation problems that has just occured prevents the max results from bounding the correct values. (RC-008) **************************************** Report : timing -path full -delay max -max_paths 1 Design : or1200_top Version: 2001.08 Date : Mon Apr 14 20:19:26 2003 **************************************** Startpoint: dwb_ack_i (input port) Endpoint: or1200_cpu/or1200_ctrl/id_insn_reg[21] (rising edge-triggered flip-flop clocked by clk_i) Path Group: clk_i Path Type: max Point Incr Path ------------------------------------------------------------------------------ clock (input port clock) (rise edge) 0.00 0.00 input external delay 3168.88 3168.88 r dwb_ack_i (in) 142.72 3311.60 r U1746/op (nand2_2) 443.72 & 3755.32 f U6773/op (inv_4) 252.45 & 4007.77 r U18833/op (nand2_2) 177.06 & 4184.83 f U17564/op (nand2_2) 461.49 & 4646.31 r U1716/op (or3_2) 462.22 & 5108.54 r U18835/op (nand2_2) 191.78 & 5300.32 f U5746/op (nand2_2) 105.81 & 5406.13 r U1504/op (nand3_2) 2112.44 & 7518.57 f U5264/op (nor2_2) 1367.36 & 8885.93 r U1754/op (nand3_2) 1095.87 & 9981.80 f U5747/op (inv_2) 488.19 & 10469.99 r U510/op (buf_2) 891.89 & 11361.88 r U17585/op (nand3_2) 958.16 & 12320.04 f U18839/op (inv_2) 231.02 & 12551.06 r U465/op (and3_2) 432.30 & 12983.36 r U1392/op (nand2_2) 275.33 & 13258.69 f U17713/op (nand2_2) 202.19 & 13460.88 r U18757/op (inv_2) 123.30 & 13584.18 f U17714/op (nand3_2) 127.39 & 13711.58 r U18782/op (inv_2) 103.81 & 13815.39 f U19431/op (nand3_2) 105.68 & 13921.07 r U17757/op (nand2_2) 1730.22 & 15651.29 f U17748/op (nand3_2) 985.65 & 16636.93 r U1471/op (inv_2) 2107.44 & 18744.37 f U2306/op (nand2_2) 604.01 & 19348.38 r U4614/op (nand2_2) 1324.82 & 20673.20 f U7382/op (inv_4) 1014.75 & 21687.96 r U4619/op (nand2_2) 2216.14 & 23904.10 f U7385/op (inv_4) 443.20 & 24347.30 r U7384/op (inv_4) 865.05 & 25212.35 f U3995/op (nor3_2) 853.66 & 26066.01 r U1709/op (or3_2) 194.28 & 26260.29 r or1200_cpu/or1200_ctrl/id_insn_reg[21]/ip (drp_2) 0.14 & 26260.43 r data arrival time 26260.43 clock clk_i (rise edge) 40000.00 40000.00 clock network delay (propagated) 2336.80 42336.80 clock uncertainty -552.00 41784.80 or1200_cpu/or1200_ctrl/id_insn_reg[21]/ck (drp_2) 41784.80 r library setup time -173.52 41611.28 data required time 41611.28 ------------------------------------------------------------------------------ data required time 41611.28 data arrival time -26260.43 ------------------------------------------------------------------------------ slack (MET) 15350.85 Startpoint: dwb_ack_i (input port) Endpoint: dwb_biu/wb_adr_o_reg[16] (rising edge-triggered flip-flop clocked by dwb_clk_i) Path Group: dwb_clk_i Path Type: max Point Incr Path --------------------------------------------------------------- clock (input port clock) (rise edge) 0.00 0.00 input external delay 3327.28 3327.28 f dwb_ack_i (in) 131.93 3459.21 f U1746/op (nand2_2) 290.10 & 3749.31 r U6773/op (inv_4) 170.23 & 3919.54 f U18833/op (nand2_2) 100.23 & 4019.77 r U17564/op (nand2_2) 703.76 & 4723.53 f U1716/op (or3_2) 858.75 & 5582.28 f U7234/op (inv_4) 312.28 & 5894.56 r U4530/op (nand3_2) 1259.45 & 7154.00 f U4397/op (mux2_2) 1180.36 & 8334.36 f U7013/op (inv_4) 41.80 & 8376.16 r U4531/op (nand2_2) 803.65 & 9179.81 f U7216/op (inv_4) 992.28 & 10172.10 r U5665/op (nand2_2) 1279.72 & 11451.82 f U7219/op (inv_4) 996.68 & 12448.50 r U4890/op (mux2_2) 744.24 & 13192.75 f dwb_biu/wb_adr_o_reg[16]/ip (drp_2) 0.28 & 13193.03 f data arrival time 13193.03 clock dwb_clk_i (rise edge) 40000.00 40000.00 clock network delay (propagated) 2402.81 42402.81 clock uncertainty -552.00 41850.81 dwb_biu/wb_adr_o_reg[16]/ck (drp_2) 41850.81 r library setup time -409.56 41441.25 data required time 41441.25 --------------------------------------------------------------- data required time 41441.25 data arrival time -13193.03 --------------------------------------------------------------- slack (MET) 28248.22 1 **************************************** Report : timing -path full -delay min -max_paths 1 Design : or1200_top Version: 2001.08 Date : Mon Apr 14 20:19:26 2003 **************************************** Startpoint: dwb_ack_i (input port) Endpoint: or1200_dc_top/or1200_dc_fsm/cnt_reg[1] (rising edge-triggered flip-flop clocked by clk_i) Path Group: clk_i Path Type: min Point Incr Path ------------------------------------------------------------------------------ clock (input port clock) (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 input external delay 3327.28 3327.28 f dwb_ack_i (in) 131.93 3459.21 f U1746/op (nand2_2) 290.10 & 3749.31 r U4750/op (or3_2) 303.53 & 4052.84 r U7281/op (inv_4) 108.23 & 4161.07 f U6314/op (nand2_2) 104.22 & 4265.28 r U1740/op (nand2_2) 129.49 & 4394.77 f or1200_dc_top/or1200_dc_fsm/cnt_reg[1]/ip (drp_2) 0.06 & 4394.83 f data arrival time 4394.83 clock clk_i (rise edge) 0.00 0.00 clock network delay (propagated) 2250.45 2250.45 clock uncertainty 552.00 2802.45 or1200_dc_top/or1200_dc_fsm/cnt_reg[1]/ck (drp_2) 2802.45 r library hold time 0.00 2802.45 data required time 2802.45 ------------------------------------------------------------------------------ data required time 2802.45 data arrival time -4394.83 ------------------------------------------------------------------------------ slack (MET) 1592.37 Startpoint: dwb_ack_i (input port) Endpoint: dwb_biu/wb_stb_o_reg (rising edge-triggered flip-flop clocked by dwb_clk_i) Path Group: dwb_clk_i Path Type: min Point Incr Path --------------------------------------------------------------- clock (input port clock) (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 input external delay 3168.88 3168.88 r dwb_ack_i (in) 142.72 3311.60 r U6630/op (inv_4) 95.72 & 3407.32 f U18666/op (nand2_2) 115.64 & 3522.96 r U18667/op (inv_2) 55.20 & 3578.16 f dwb_biu/wb_stb_o_reg/ip (drp_2) 0.10 & 3578.26 f data arrival time 3578.26 clock dwb_clk_i (rise edge) 0.00 0.00 clock network delay (propagated) 2320.09 2320.09 clock uncertainty 552.00 2872.09 dwb_biu/wb_stb_o_reg/ck (drp_2) 2872.09 r library hold time 0.00 2872.09 data required time 2872.09 --------------------------------------------------------------- data required time 2872.09 data arrival time -3578.26 --------------------------------------------------------------- slack (MET) 706.16 1