Preliminary Clock-Tree Analysis
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Design: or1200_top
Clock Source: clk_i
Total Sinks: 1136
Min Delay: 2238.26
Max Delay: 2544.99
Skew: 306.73
Last Stage Drivers: 287
Min Transition Time: 212.386566
Max Transition Time: 317.238037
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Design: or1200_top
Clock Source: dwb_clk_i
Total Sinks: 73
Min Delay: 2313.52
Max Delay: 2437.96
Skew: 124.44
Last Stage Drivers: 8
Min Transition Time: 382.366821
Max Transition Time: 471.813324
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Design: or1200_top
Clock Source: iwb_clk_i
Total Sinks: 73
Min Delay: 2103.38
Max Delay: 2262.04
Skew: 158.66
Last Stage Drivers: 20
Min Transition Time: 291.287262
Max Transition Time: 456.532471
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Design: uart_top
Clock Source: wb_clk_i
Total Sinks: 606
Min Delay: 2546.33
Max Delay: 2653.76
Skew: 107.43
Last Stage Drivers: 48
Min Transition Time: 458.222748
Max Transition Time: 551.914490