Warning: Some timing arcs have been disabled for breaking timing loops or because of constant propagation. Use the 'report_disable_timing' command to get the list of these disabled timing arcs. (PTE-003) **************************************** Report : timing -path full -delay max -max_paths 1 Design : uart_top Version: 2001.08 Date : Mon Apr 14 20:19:46 2003 **************************************** Startpoint: wb_adr_i[3] (input port) Endpoint: wb_interface/wb_adr_is_reg[1] (rising edge-triggered flip-flop clocked by wb_clk_i) Path Group: wb_clk_i Path Type: max Point Incr Path ------------------------------------------------------------------------------ clock (input port clock) (rise edge) 0.00 0.00 input external delay 3044.73 3044.73 f wb_adr_i[3] (in) 11.87 3056.60 f U276/op (inv_1) 550.53 & 3607.13 r U277/op (inv_4) 142.26 & 3749.39 f U275/op (buf_1) 456.36 & 4205.75 f wb_interface/wb_adr_is_reg[1]/ip (drp_2) 5.90 & 4211.65 f data arrival time 4211.65 clock wb_clk_i (rise edge) 40000.00 40000.00 clock network delay (propagated) 2584.79 42584.79 clock uncertainty -552.00 42032.79 wb_interface/wb_adr_is_reg[1]/ck (drp_2) 42032.79 r library setup time -460.02 41572.77 data required time 41572.77 ------------------------------------------------------------------------------ data required time 41572.77 data arrival time -4211.65 ------------------------------------------------------------------------------ slack (MET) 37361.12 1 **************************************** Report : timing -path full -delay min -max_paths 1 Design : uart_top Version: 2001.08 Date : Mon Apr 14 20:19:46 2003 **************************************** Startpoint: wb_dat_i[25] (input port) Endpoint: wb_interface/wb_dat_is_reg[6] (rising edge-triggered flip-flop clocked by wb_clk_i) Path Group: wb_clk_i Path Type: min Point Incr Path ------------------------------------------------------------------------------ clock (input port clock) (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 input external delay 2801.45 2801.45 r wb_dat_i[25] (in) 11.59 2813.04 r U318/op (inv_1) 157.64 & 2970.68 f U319/op (inv_4) 45.78 & 3016.45 r U317/op (buf_1) 136.76 & 3153.22 r wb_interface/wb_dat_is_reg[6]/ip (drp_2) 0.11 & 3153.32 r data arrival time 3153.32 clock wb_clk_i (rise edge) 0.00 0.00 clock network delay (propagated) 2605.07 2605.07 clock uncertainty 552.00 3157.07 wb_interface/wb_dat_is_reg[6]/ck (drp_2) 3157.07 r library hold time 0.00 3157.07 data required time 3157.07 ------------------------------------------------------------------------------ data required time 3157.07 data arrival time -3153.32 ------------------------------------------------------------------------------ slack (VIOLATED) -3.74 1