# FirstEncounter(TM) Clock Synthesis Technology File Format
# for automatic gated clock tree synthesis
#   AutoCTSRootPin    <clock root pin name>
#   MaxDelay     <number>
#   MinDelay     <number>
#   SinkMaxTran          <number>
#   BufMaxTran   <number>
#   MaxSkew           <number>
#   NoGating          <rising|falling|NO>
#   MaxDepth     <number>
#   Buffer           <cell_1> <cell_2> <cell_3> ....
#   LeafPin
#   +  <pin name> <rising|falling>
#   +  ....
#   LeafPort
#   +  <port name> <rising|falling>
#   +  ....
#   ExcludedPin
#   +  <pin name>
#   +  ....
#   ExcludedPort
#   +  <port name>
#   +  ....
#   End
#
AutoCTSRootPin    wb_clk_i
NoGating          rising
MaxDelay          3ns
MinDelay          0ns
MaxSkew           10ps
SinkMaxTran       200ps
BufMaxTran        200ps
Buffer            buf_4 buf_2 buf_1 inv_4 inv_2 inv_1
End