2005.ncsu.edu.3DIC.Phase1
3DIC Phase 1 Place & Route Flow
Version 1.0
This flow represents a current snapshot of the 3DIC Design Flow used to
generate the FFT design described in the article
"Demystifying 3D-IC's: The Pros and Cons of Going Vertical", to appear
in IEEE Design and Test of Computers. This design-flow is not
yet supported but is documented here for the purpose of soliciting comments.
Future versions of this documentation will include bug-fixes and greater
detail about various parts of the flow.
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