-----------------------------------------------------------------------------
-- Entity:      tworeg_slave
-- File:        tworeg_slave.vhd
-- Author:      Ambarish Sule (amsule@ncsu.edu)
-- Description: This unit is intended to be an AMBA-compliant slave module,
--              having 2 32-bit registers
------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use work.target.all;
use work.config.all;
use work.iface.all;
use work.amba.all;                      -- AMBA Bus definitions

entity tworeg_slave is
  port (
    rst  : in  std_logic;               -- Reset Input for the module
    clk  : in  clk_type;                -- Clock Input for the module
    -- Look for the AMBA bus descriptions in the leon/amba.vhd file
    apbi : in  apb_slv_in_type;         -- Uses the AMBA APB Slave Input Signals
    apbo : out apb_slv_out_type        -- Uses the AMBA APB Slave Output Signals
    ); 
end tworeg_slave;


architecture rtl of tworeg_slave is
  -- The 2 32-bit registers in the design
  signal REG0 : std_logic_vector(31 downto 0) := (others => '0');
  signal REG1 : std_logic_vector(31 downto 0) := (others => '0');

begin  -- rtl

regprocess: process (clk, rst)
  variable rdata      : std_logic_vector(31 downto 0);  -- 32-bit Read Data bus
begin  -- process regprocess

  if (rst = '0') then                     -- asynchronous reset (active low)
    -- Clear the contents of the registers
    REG0 <= (others => '0');
    REG1 <= (others => '0');

  elsif (clk'event and clk = '1') then    -- rising clock edge
    -- Write into the registers only if all the psel, penable and pwrite
    -- signals are '1' (Section 5.2.2 Pg.171 of AMBA Protocol)
    if (apbi.psel and apbi.penable and apbi.pwrite) = '1' then
      case apbi.paddr(5 downto 2) is    -- 32-bit transfers, hence paddr(1 downto 0) ignored
        when "0000" => REG0 <= apbi.pwdata(31 downto 0);
        when "0001" => REG1 <= apbi.pwdata(31 downto 0);
        when others => null;
      end case;
    end if;

    -- The Read data bus is always driven irrespective of
    -- the psel and penable signals
    rdata := (others => '0');
    case apbi.paddr(5 downto 2) is
      when "0000" => rdata := REG0;
      when "0001" => rdata := REG1;
      when others => null;
    end case;
    
    apbo.prdata <= rdata;

  end if; -- elsif (clk'event and clk = '1')
  
end process regprocess;

end rtl;