3DIC Project
UNIX Modelsim Simulator Tutorial
Modelsim is an Verilog/VHDL HDL simulator from Model Technology, a Mentor Graphics company.
This Tutorial is intended as a "getting-started" guide to Modelsim Simulations on UNIX Machines in the EOS Environment.
- Login to a UNIX Machine in any EOS Lab. If you login to a remote machine from a PC, make sure to start X-win32 and setenv the appropriate DISPLAY variable. For eg, if your PC is named fever.ecew2k.ncsu.edu, type "setenv fever.ecew2k.ncsu.edu:0.0" on the UNIX prompt.
- Create a new directory, eg. "modelsim_tut". "cd" to this directory. Copy the following files into this directory:
- test.vhd - VHDL Testbench Source Code
- duv.vhd - VHDL Device under Verification (An AND Gate)
- duv.v - Verilog Device under Verification (An AND Gate)
- modelsim.ini - Modelsim Initialization or Configuration File
- Take a moment to read through these files. test.vhd contains the VHDL Testbench which instantiates the 2 AND gates declared in duv.vhd and duv.v and stimulates them.
- modelsim.ini is the Configuration file for Modelsim. The important line to note here is the "work = ./modelsim_work" line in the [Library] Section. This indicates that the logical "work" library will be mapped to the physical "modelsim_work" library. Thus, whenever the VHDL code refers to "library work; use work.all;", Modelsim will start looking for the corresponding files in the modelsim_work directory.
- On the Unix Prompt, execute the following commands:
- add modelsim
- setenv MODELSIM modelsim.ini
- Now we need to create the physical "modelsim_work" directory which Modelsim will use to store its internal representation of our HDL Designs. Make sure you are in directory "modelsim_tut". Execute "vlib modelsim_work".
Warning: Never use "mkdir modelsim_work" to create this directory. - Compile the HDL files. Use "vlog" to compile the Verilog code and "vcom" to compile VHDL code. Execute:
- vlog duv.v
- vcom duv.vhd
- vcom test.vhd
- Now that the HDL files have been compiled, its time to Simulate! Note that "test_top" is the Top Entity in the entire HDL design and Testbench hierarchy. Hence execute "vsim test_top". This will open the Modelsim GUI. All further commands have to be typed at the VSIM N> Prompt. Here N indicates the number of commands typed at the prompt. It will increase after every command at the prompt.
- Execute "log -r /*". This will log the values of all the signals in the design, to be viewed later as a waveform. It is analogous to calling "$dumpvars" in a Verilog file. Beware that signal logging could slow down simulations in very large designs.
- Click on View->Wave on the menu bar. This will open a Waveform window. It is currently blank.
Signals to be viewed can be inserted in this window as follows: In the left portion of the main Modelsim window, click on the graphic indicating "test_top:test_top(behavioral)" and without releasing the mouse, drag-and-drop it to the left side of the Waveform window. You should be able to see 6 signals (from the entity test_top) in the waveform window. In a similar manner, any other signals could be viewed. - Execute "run 100ns".
Never execute "run -all". VHDL has no equivalent of "$finish" as in Verilog. The waveform window should reflect the changed signals. Correlate with the stimulus in the test.vhd file.
Verify that both the DUVs are indeed AND gates. Keep running for as much time as you want. - Try View->All in the Modelsim window and play around with the different windows that pop up.
- For help, click on Help->SE (PDF/HTML) Documentation.
It contains a Tutorial and all Reference Documentation.
This tutorial can also be viewed at: (Windows, Unix) - Execute "restart" to restart the simulation or "exit -f" to exit Modelsim
Congratulations! You can now start using Modelsim.
Some useful VHDL references can be found at:
http://www.vhdl-online.de/
http://tech-www.informatik.uni-hamburg.de/vhdl/
http://www.doulos.com/fi/
http://www.acc-eda.com/vhdlref/