/********************************************************
 *
 * UNIX Modelsim Tutorial
 *
 * Simple Verilog Module (An AND Gate)
 * 
 * Author : Ambarish Sule (amsule@unity.ncsu.edu)
 *
 ********************************************************/


module VER_DUV (Ain, Bin, Cout);

   input Ain;
   input Bin;
   output Cout;

   assign Cout=(Ain&Bin);

endmodule // VER_DUV