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-- UNIX Modelsim Tutorial
--
-- Simple VHDL entity (An AND Gate)
--
-- Author : Ambarish Sule (amsule@unity.ncsu.edu)
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library ieee; -- similar to #include in C
use ieee.std_logic_1164.all;

-- Declare the ports if any
entity VHDL_DUV is
  port (
    Ain  : in  std_logic;
    Bin  : in  std_logic;
    Cout : out std_logic                -- No ";"
    );
end VHDL_DUV;

architecture BEHAVIORAL of VHDL_DUV is
begin
  Cout <= (Ain AND Bin);
end;